Binary Reachability of Timed-register Pushdown Automata and Branching Vector Addition Systems (original) (raw)

Timed pushdown automata and branching vector addition systems

2017 32nd Annual ACM/IEEE Symposium on Logic in Computer Science (LICS), 2017

The version presented here may differ from the published version or, version of record, if you wish to cite this item you are advised to consult the publisher's version. Please see the 'permanent WRAP url' above for details on accessing the published version and note that access may require a subscription.

Binary reachability of timed pushdown automata via quantifier elimination and cyclic order atoms

2018

We study an expressive model of timed pushdown automata extended with modular and fractional clock constraints. We show that the binary reachability relation is effectively expressible in hybrid linear arithmetic with a rational and an integer sort. This subsumes analogous expressibility results previously known for finite and pushdown timed automata with untimed stack. As key technical tools, we use quantifier elimination for a fragment of hybrid linear arithmetic and for cyclic order atoms, and a reduction to register pushdown automata over cyclic order atoms.

Reachability Problem for Weak Multi-Pushdown Automata

Logical Methods in Computer Science, 2013

This paper is about reachability analysis in a restricted subclass of multipushdown automata. We assume that the control states of an automaton are partially ordered, and all transitions of an automaton go downwards with respect to the order. We prove decidability of the reachability problem, and computability of the backward reachability set. As the main contribution, we identify relevant subclasses where the reachability problem becomes NP-complete. This matches the complexity of the same problem for communication-free vector addition systems, a special case of stateless multipushdown automata. 2012 ACM CCS: [Theory of computation]: Models of computation; Formal languages and automata theory-Formalisms-Rewrite systems; Semantics and reasoning-Program reasoning-Program verification.

Timed Pushdown Automata Revisited

2015 30th Annual ACM/IEEE Symposium on Logic in Computer Science, 2015

This paper contains two results on timed extensions of pushdown automata (PDA). As our first result we prove that the model of dense-timed PDA of Abdulla et al. collapses: it is expressively equivalent to dense-timed PDA with timeless stack. Motivated by this result, we advocate the framework of firstorder definable PDA, a specialization of PDA in sets with atoms, as the right setting to define and investigate timed extensions of PDA. The general model obtained in this way is Turing complete. As our second result we prove NEXPTIME upper complexity bound for the non-emptiness problem for an expressive subclass. As a byproduct, we obtain a tight EXPTIME complexity bound for a more restrictive subclass of PDA with timeless stack, thus subsuming the complexity bound known for dense-timed PDA.

Multi-Core Reachability for Timed Automata

2012

Model checking of timed automata is a widely used technique. But in order to take advantage of modern hardware, the algorithms need to be parallelized. We present a multi-core reachability algorithm for the more general class of well-structured transition systems, and an implementation for timed automata.

FO2(<,+1,~) on data trees, data tree automata and branching vector addition systems

Logical Methods in Computer Science, 2016

A data tree is an unranked ordered tree where each node carries a label from a finite alphabet and a datum from some infinite domain. We consider the two variable first order logic FO 2 (<, +1, ∼) over data trees. Here +1 refers to the child and the next sibling relations while < refers to the descendant and following sibling relations. Moreover, ∼ is a binary predicate testing data equality. We exhibit an automata model, denoted DTA # , that is more expressive than FO 2 (<, +1, ∼) but such that emptiness of DTA # and satisfiability of FO 2 (<, +1, ∼) are inter-reducible. This is proved via a model of counter tree automata, denoted EBVASS, that extends Branching Vector Addition Systems with States (BVASS) with extra features for merging counters. We show that, as decision problems, reachability for EBVASS, satisfiability of FO 2 (<, +1, ∼) and emptiness of DTA # are equivalent.

The Power of Reachability Testing for Timed Automata

Lecture Notes in Computer Science, 1998

The computational engine of the veriÿcation tool UPPAAL consists of a collection of e cient algorithms for the analysis of reachability properties of systems. Model-checking of properties other than plain reachability ones may currently be carried out in such a tool as follows. Given a property to model-check, the user must provide a test automaton T for it. This test automaton must be such that the original system S has the property expressed by precisely when none of the distinguished reject states of T can be reached in the synchronized parallel composition of S with T. This raises the question of which properties may be analysed by UPPAAL in such a way. This paper gives an answer to this question by providing a complete characterization of the class of properties for which model-checking can be reduced to reachability testing in the sense outlined above. This result is obtained as a corollary of a stronger statement pertaining to the compositionality of the property language considered in this study. In particular, it is shown * Corresponding author.

A linear time extension of deterministic pushdown automata

2009

A linear time extension of deterministic pushdown automata is introduced that recognizes all deterministic context-free languages, but also languages such as {a n b n c n | n ≥ 0} and the MIX language. It is argued that this new class of automata, called λ-acyclic read-first deterministic stack+bag pushdown automata, has applications in natural language processing. * Thanks to Thomas Hanneforth for pointing out previous work on φ-transitions to me.

Reachability analysis for timed automata using max-plus algebra

The Journal of Logic and Algebraic Programming, 2012

We show that max-plus polyhedra are usable as a data structure in reach-ability analysis of timed automata. Drawing inspiration from the extensive work that has been done on difference bound matrices, as well as previ-ous work on max-plus polyhedra in other areas, we ...

Descriptional complexity of two-way pushdown automata with restricted head reversals

Theoretical Computer Science, 2012

Two-way nondeterministic pushdown automata (2PDA) are classical nondeterministic pushdown automata (PDA) enhanced with two-way motion of the input head. In this paper, the subclass of 2PDA accepting bounded languages and making at most a constant number of input head turns is studied with respect to descriptional complexity aspects. In particular, the effect of reducing the number of pushdown reversals to a constant number is of interest. It turns out that this reduction leads to an exponential blow-up in case of nondeterministic devices, and to a doubly-exponential blow-up in case of deterministic devices. If the restriction on boundedness of the languages considered and on the finiteness of the number of head and pushdown turns is dropped, the resulting trade-offs are no longer bounded by recursive functions, and so-called non-recursive trade-offs are shown.