IJERT-Simulation Of Bridgeless Buck PFC Converter (original) (raw)

IJERT-Analysis of Bridgeless PFC Boost Converter

International Journal of Engineering Research and Technology (IJERT), 2012

https://www.ijert.org/analysis-of-bridgeless-pfc-boost-converter https://www.ijert.org/research/analysis-of-bridgeless-pfc-boost-converter-IJERTV1IS5373.pdf Conventional boost PFC converter has disadvantage having high conduction loss in the rectifier-bridge. Bridgeless PFC boost converter reduces conduction loss and improves efficiency by omitting rectifier-bridge. This converter has advantages like reduced conduction loss, reduced hardware and high performance. This paper presents simulation of bridgeless PFC boost converter, also called dual boost PFC rectifier. This bridgeless PFC circuit has much higher common mode EMI than conventional PFC circuit. Common mode EMI is reduced by adding slow recovery diodes in bridgeless PFC circuit. Power factor is more improved by adding capacitor in parallel with AC source.

Novel Zero-Voltage-Switching Bridgeless PFC Converter

Journal of power electronics

In this paper, a new zero-voltage-switching, high power-factor, bridgeless rectifier is introduced. In this topology, an auxiliary circuit provides soft switching for all of the power semiconductor devices. Thus the switching losses are reduced and the highest efficiency can be achieved. The proposed converter has been analyzed and a design procedure has been introduced. The control circuit for the converter has also been developed. Based on the given approach, a 250 W, 400 Vdc prototype converters has been designed at 100 kHz for universal input voltage (90-264 Vrms) applications. A maximum efficiency of 94.6% and a power factor correction over 0.99 has been achieved. The simulation and experimental results confirm the design procedure and highlight the advantages of the proposed topology.

IJERT-A novel control method for bridgeless voltage doubler pfc buck converter IJERTV2IS

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/a-novel-control-method-for-bridgeless-voltage-doubler-pfc-buck-converter https://www.ijert.org/research/a-novel-control-method-for-bridgeless-voltage-doubler-pfc-buck-converter-IJERTV2IS101004.pdf Switch mode power supplies without Power Factor Correction (PFC) tend to draw the AC line current in a non-linear fashion and may generate many unwanted harmonic content in the input current waveform. This leads to a very low power factor and less efficiency. The reason for the low and non-linear PF is that the AC input of a high frequency switched-mode conversion circuit consists of a diode bridge rectifier followed by bulk storage capacitor, This low power factor can be improved by using power factor correction circuit along with the rectifier circuit. A bridgeless Buck Converter can be used as a power factor correction circuit as well as a voltage doubler circuit for switched mode power supplies. This topology also have lesser number of conducting devices than the conventional bridge rectifier and buck converter, due to which it is having lesser conduction and switching losses. The voltage output of this circuit is also double the voltage produced by a single buck converter used as pfc circuit. A new control method called One Cycle control is introduced in this paper for the control of this circuit. This is a non linear control technique and produce faster response than the clamped mode current control. The simulation of bridgeless Buck converter using this control method is presented in this paper

Soft Switching Bridgeless PFC Buck Converters

Journal of Power Electronics, 2012

Based on the standards that limit the harmonic pollution of electronic systems, the use of PFC converters is mandatory. In this paper, a new resonant bridgeless PFC converter is introduced. By eliminating the input bridge diodes, the efficiency is improved. Moreover, soft switching conditions for all of the semiconductor elements are achieved without adding any extra switches. As a result, high efficiency is attained. The proposed converter is analyzed and the theoretical and simulation results of the proposed converter are presented. In order to verify the validity of the analysis, a 40 w prototype converter is implemented and experimental results are presented. The experimental results show that high efficiency is attained while achieving a high power factor.

POWER FACTOR CORRECTION BY BRIDGELESS BUCK BOOST CONVERTER

IAEME Publication, 2020

In current Scenario, efficiency and economic are the major concerns in designing and developing low-power applications. The aim of the paper is to design a Bridge Less Power Factor Corrected (BLPFC) buck boost converter for low power applications. The diode bridge is eliminating using bridgeless configuration thus reducing the conduction losses associate with in it. A BLPFC buck boost converter is design to operate in Discontinuous Current Mode (DCM) to provide a better Power Factor Correction (PFC) at AC mains. The PI controller design will be used to reduce the harmonics present in the system and to maintain the unity power factor at different voltages. This drive is to compare with the different input voltages and shows satisfactory performance. The performance of the system is to be simulated using MATLAB/Simulink. The experimental output values will be tabulated and the system is maintaining unity power factor at various voltages (90V, 100V, 125V).

IJERT-Performance Evaluation of Bridgeless High Power Factor Buck Front End

International Journal of Engineering Research and Technology (IJERT), 2014

https://www.ijert.org/performance-evaluation-of-bridgeless-high-power-factor-buck-front-end https://www.ijert.org/research/performance-evaluation-of-bridgeless-high-power-factor-buck-front-end-IJERTV3IS040502.pdf This paper focuses a bridgeless buck converter providing high power factor and thereby improves the efficiency of the buck front end. The proposed buck PFC rectifier also act as a voltage doubler, whose output voltage is twice that of a conventional Buck PFC rectifier. The proposed buck PFC rectifier uses fewer components when compared with previous buck topology. The performance comparison between the conventional buck PFC rectifier and the bridgeless PFC buck rectifiers are performed by simulating them in PSIM. Index Terms-Buck converter, Power factor correction (PFC), Bridgeless Ι. INTRODUCTION Performance and efficiency of converters is increased by high power factor and low current distortion. By introducing some form of PFC circuits, the requirement of high power factor is usually achieved. Maintaining a high efficiency across the entire line ranges poses a major challenge in ac/dc converters that require power factor correction (PFC). At the earlier stage the boost topology was widely used. The output voltage of the boost converter is greater than input. This fact leads to the use of higher rating semiconductor device at the dc-dc output stages. By implementing buck PFC topology, the drawback of boost PFC rectifier can be overcome. Conventional Buck PFC rectifier comprises of full bridge rectifier followed by a buck converter. Conventional buck PFC rectifier suffers from high conduction losses and switching losses due to the presence of input rectifier bridge. To reduce this, a bridgeless configuration [2] was introduced which eliminates the use of diode bridge rectifier .Through the minimization of simultaneously conducting components, the proposed PFC rectifier enhances the low line efficiency of buck front end. The proposed rectifier also works as a voltage doubler circuit whose output voltage is twice that of a conventional buck PFC rectifier. The switching losses of primary switches of downstream dc/dc stages are still lower than that of boost PFC, though the output voltage across the load is doubled. The modified bridgeless PFC rectifier further improves the efficiency and power factor with reduced ripple content. Also this configuration uses one capacitor. Thereby reduce its cost. Following the introduction, the proposed topology is given in section ΙΙI, the modified bridgeless buck topology is given in section ΙV. Section V provides simulation results to validate the analysis. Finally, conclusions are given in section VI. ΙΙ. CONVENTIONAL BUCK PFC RECTIFIER Fig.1. Conventional buck PFC rectifier. Conventional buck PFC converters consist of a full bridge diode rectifier followed by buck converter. When the switch is closed, the DC source supplies power to the circuit and it gives rise to an output voltage across the resistor. When the switch is opened, the energy stored in the inductor and capacitor discharges through the resistor. By controlling the duty ratio appropriately a desired value of output voltage, lower than the input voltage can be obtained. It has drawback having high conduction losses in the rectifier bridge.

A New High Efficiency High Power Factor ZVT Bridgeless PFC Converter

Hamid Torkkhah, 2016

In this paper, a new zero voltage transition (ZVT) bridgeless PFC converter with high power factor and high efficiency is presented. The proposed converter has not any extra voltage stresses on semiconductor elements. Main switches of converter are switched under zero voltage (ZV) condition. Also the auxiliary switch is turned on under zero current (ZC) and turned off under zero voltage and current (ZVZC) condition. Due to use of bridgeless topology and soft switching technique simultaneously the converter's efficiency is higher than conventional counterpart. Also the proposed converter does not need the float gate driver. The operation of proposed converter is analyzed theoretically and the operation modes are presented. The design considerations are explained by a design example. The proposed converter is simulated by PSIM software to show the validity of theoretical analysis. The simulation results are compared with theoretical waveforms. The efficiency simulation in ORCAD software shows 2% efficiency improvement in comparison with conventional PFC boost converter.

Bridgeless boost PFC converter using the three-state switching cell

Eletrônica de Potência, 2012

This paper introduces a bridgeless boost converter based on the three-state switching cell for PFC (power factor correction) applications, whose distinct advantages are reduced conduction losses with the use of magnetic elements with minimized size, weight, and volume. The approach also employs the principle of interleaved converters, as it can be extended to a generic number of legs per winding of the autotransformers and high power levels. The theoretical analysis of the proposed converter is developed, while a comparison with the conventional boost converter is also performed. An experimental prototype rated at 1 kW is implemented to validate the proposal, as relevant issues regarding the novel converter are discussed. 1 I. INTRODUCTION

JPE 13-1-5 Novel Zero-Voltage-Switching Bridgeless PFC Converter

2013

In this paper, a new zero-voltage-switching, high power-factor, bridgeless rectifier is introduced. In this topology, an auxiliary circuit provides soft switching for all of the power semiconductor devices. Thus the switching losses are reduced and the highest efficiency can be achieved. The proposed converter has been analyzed and a design procedure has been introduced. The control circuit for the converter has also been developed. Based on the given approach, a 250 W, 400 Vdc prototype converters has been designed at 100 kHz for universal input voltage (90-264 Vrms) applications. A maximum efficiency of 94.6% and a power factor correction over 0.99 has been achieved. The simulation and experimental results confirm the design procedure and highlight the advantages of the proposed topology.

Single‐stage PFC bridgeless converter

Electronics Letters, 2020

A power factor correction (PFC) charge-pump (CP) bridgeless converter for LEDs is presented. In the input stage, coupled inductors, together with CP capacitors, are integrated into a half-bridge inverter, thus characterising the single stage. This topology even being bridgeless due to the positioning of the load operates with a bus voltage below the bending voltage. The CP configuration is used to reduce the LED's current ripple. The prototype achieves an output power of 60 W with high power factor, achieving the efficiency of up to 94%, 127 V ac input, total harmonic distortion of input current, with harmonic magnitudes within the IEC 61000-3-2 standard class C the device limits and flicker in conformed with the recommendation of IEEE 1789.