A 1.1 V 6.2 mW, wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS (original) (raw)
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A 0.5–6GHz low gain linear RF front-end in 90nm CMOS
2010
This paper presents the design and measurement results of low gain RF front-end manufactured in 90nm CMOS covering the frequency range of 0.5-6GHz. The front-end is a modified form of a balanced active mixer to enhance its gain and achieve wideband input matching. The transconductance stage of a mixer is split into NMOS-PMOS inverter pair for better linearity and partial noise cancellation. The inverter stage with common drain feedback achieves wideband input impedance match better than −8dB up to 8GHz. The voltage conversion gain is 5dB at 6GHz with 3dB bandwidth of more than 5.5GHz. The measured single side band noise figure at LO frequency of 1.5GHz and IF of 30MHz is 7dB. The measured 1dB compression point is -17dBm at 2.4GHz. Similarly, measured IIP3 is 2.5dBm and IIP2 is 40dBm at 1GHz. The complete front-end consumes 23mW with active chip area of only 0.048mm 2 .
This paper presents the design of a 1.5 V CMOS RF receiver front-end system which contains a low noise amplifier (LNA) with band pass filter and a down conversion mixer. An inter-stage matching network is added between the common-source and common-gate transistors in the LNA's first stage to further lower the noise and enhance the overall gain. An inductor is used in this inter-stage matching network because of the extra capacitive of MOSFETs in the LNA. The maximum gain achieved of this LNA is 15 dB. The single square-law structure was implemented for this low power consumption and high linearity mixer. From the measured results, the whole receiver provides a conversion gain of 8.5 dB at 2.4 GHz with LO power input -3.5 dBm. The power dissipation of this front-end is 9 mW .
International Journal of Circuit Theory and Applications
This paper presents an integrated wideband RF front-end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common-gate common-source low noise amplifier (CG-CS LNA) with capacitive feedback, together with an N-path filtering load. The capacitive feedback across the LNA ensures that the selective N-path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front-end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented which leads to clear design guidelines. Evaluated in a 28nm fully-depleted silicon-on-insulator CMOS process, front-end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11mA current from a 1V supply (excluding LO buffering) and possess a maximum NF of 5.1dB. The front-end demonstrates an out-of-band blocker compression point (BCP) of-1.5dBm and out-of-band IIP3 of +14dBm at a 100MHz offset from local oscillator frequency. In comparison to a traditional CG-CS LNA based front-end with wideband input impedance matching, the proposed front-end achieves 3.5dB improvement in the BCP at a 100MHz offset from LO.
A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance
2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
This paper presents a class-AB sub-GHz RF receiver front-end suitable for ultra-low power application. By exploiting transistors' class-AB operation in both the RF and baseband sections, the receiver front-end achieves a very low sensitivity and an elevated blocker tolerance while keeping a low power consumption. Such performance makes the receiver suitable for both short-range (e.g. 802.15.4) and long-range (e.g. LoRa) applications. The proposed RF front-end has been implemented in 0.13um CMOS technology, operates in the 868/915MHz ISM bands, and exhibits an in-band gain of 50dB, noise figure of 2.7dB, out-of-band HP3 of +2dBm, out-of-band IIP2 of +37dBm, out-of-band P1dB of −10.5dBm, while draining 2.1mA from a 1.2 V supply.
Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications
IEE Proceedings - Circuits, Devices and Systems, 2002
A fully integrated low-voltage R F receiver front end for 5 GHz radio applications, implemented in a standard 0.18 pm CMOS technology, is presented. The receiver consists of a differential low noise amplifier, an active mixer, and a quadrature voltage-controlled oscillator. The complete receiver is packaged in a standard 24-pin ceramic flat pack and consumes 56 mW from a 0.8V supply. Measurement results show that the receiver has an overall noise figure of 7dB, a-1 dBm input-referred 11P3, and 22 dB of image rejection. A stand-alone single-ended version of the LNA is also presented. Simple mechanisms for tuning the gain and the centre frequency of the LNA are proposed. With a supply voltage of 1 V, the LNA provides a power gain of 13.2 dB, has a noise figure of 2.5 dB, and over 10 dB of gain control and 360 MHz of frequency tuning. The LNA still operates well from a supply voltage as low as 0.7 V, providing a power gain of 7 dB.
Wideband CMOS RF front-end receiver with integrated filtering
2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES), 2015
A wideband CMOS receiver front-end for radio applications operating between 300 MHz and 900 MHz is presented. In order to obtain channel selection with image-rejection and outof-band interferers attenuation, both low-noise amplifier (LNA) and mixer incorporate a N-Path signal processing technique. The effectiveness of this N-Path filtering is investigated by comparing distinct combinations of clock phases and respective duty cycle. Using a standard 130 nm CMOS technology and a supply voltage of 1.2 V, it was possible to obtain a voltage gain greater than 28 dB, a noise figure (NF) lower than 6.05 dB and IIP3 >-1.54 dBm.
A merged LNA and mixer with improved noise figure and gain for software defined radio applications
IEICE Electronics Express, 2012
This letter presents a new architecture of merged low noise amplifier and mixer, which employs a noise cancellation scheme and uses an inductor as an inter-stage matching network between LNA and mixer to absorb parasitic capacitances. As the parasitic capacitances degrade the gain and noise figure of the entire circuit, using an inductor in the inter-stage can very effectively improve both noise figure and gain of the circuit. Based on this new method, a merged LNA-mixer has been designed in a 0.18-μm RF CMOS technology. Simulation results show 4-dB increase in power conversion gain and 1.7-dB improvement in noise figure in comparison with the case without inter-stage filter. This circuit draws only 5 mA from a 1.8 V supply and covers the frequency range of 1.3 GHz to 4.1 GHz. Its large bandwidth as well as low power consumption makes it suitable for rapidly growing software defined radio RF transceivers.
A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS
IEEE J. Semiconductor Technology and …, 2011
A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 m CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/low-power-design-and-analysis-of-low-noise-amplifiers-for-rf-receiver-front-end-using-90nm-cmos https://www.ijert.org/research/low-power-design-and-analysis-of-low-noise-amplifiers-for-rf-receiver-front-end-using-90nm-cmos-IJERTV2IS100924.pdf This letter presents the design of low-noise amplifiers for wireless receiver front ends. Several low noise amplifier topologies are implemented namely: (1) cascaded common-source amplifier, (2) folded cascode amplifier, (3) shunt feedback amplifier and (4) Current-Reuse g m boosted CG LNA. The amplifiers were implemented in a standard 90-nm CMOS process and were operated with a 1-V supply voltage. Low-noise amplifier measurements were taken for parameters such as power gain, noise figure, input matching, output matching, reverse isolation, stability, and linearity. Based on the employed figure-of-merit, the cascoded commonsource low-noise amplifier achieved the best performance among the four with a simulated gain of 13.8 dB and noise figure of 1.7 dB, which makes it comparable to previously available works.
A 0.8 GHz to 1 GHz 0.25 μm CMOS low noise amplifier for multi-standard receiver
2007 International Conference on Intelligent and Advanced Systems, 2007
A single-ended low noise amplifier (LNA) for a multi-standard (800 to 1000 MHz) mobile receiver that covers GSM and 3G respectively, has been designed and simulated in a 0.25 μm CMOS technology process. This LNA makes part of a larger system to cover GSM and 3G bands from 800 to 2100 MHz but this work only focuses on lower bands. The circuit topology is based on inductively degenerated common source (IDCS). Circuit simulations indicate a power gain of 12 dB, a noise figure of 0.7 dB with IIP3 and 1-dB compression point of 0.87 dBm and-2.7 dBm respectively. The current consumption for this circuit is 8.3 mA with voltage supply of 2.5V. I.