A 0.25 μm SiGe receiver front-end for 5GHz applications (original) (raw)

A 0.25 μm SiGe receiver front-end for 5 GHz applications

This paper presents the design and measurements of a receiver front end dedicated to IEEE 802.11a WLAN applications. It consists of an integrated transformer, a low noise amplifier (LNA), a mixer and a synchronous oscillator (SO) as a frequency generation device. This front-end has a gain of 22 dBV at 5.2 GHz and a good trade off between its linearity

Low noise, high linearity, wide bandwidth amplifier using a 0.35 μm SiGe BiCMOS for WLAN applications

2002

In this paper, we present the design of an integrated low noise amplifier (LNA) for WLAN applications in the 6 GHz range using a low complexity SiGe BiCMOS technology. The SiGe HBTs used In the design feature a typical cut-off frequency "Ft" of 45 GHz and a typical maximum oscillation frequency "Fmax" of 60 GHz The LNA exhibits a 17 dB power gain with a 1.4 GHz bandwidth and a noise figure lower than 2.5 dB. The 1 dB compression point Is -18 dBm and the third order intercept point referred to the input is -7 dBm. We have furthermore observed a good accuracy between simulations and measurements. Finally, we have defined a new figure of merit involving the noise measure and the DC power consumption that shows that our design features a performance at the state of the art.

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

International Journal of Rf and Microwave Computer-aided Engineering, 2007

In this paper, a 4.2–5.4 GHz, −Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is −110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and −113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm2 on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.