High resolution pixel detectors for e+e- linear colliders (original) (raw)
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High-resolution hybrid pixel sensors for the e+e− TESLA linear collider vertex tracker
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2000
In order to fully exploit the physics potential of a future high-energy e>e\ linear collider, a Vertex Tracker, providing high-resolution track reconstruction, is required. Hybrid silicon pixel sensors are an attractive option, for the sensor technology, due to their read-out speed and radiation hardness, favoured in the high-rate environment of the TESLA e>e\ linear collider design, but have been so far limited by the achievable single point space resolution. In this paper, a conceptual design of the TESLA Vertex Tracker, based on a novel layout of hybrid pixel sensors with interleaved cells to improve their spatial resolution, is presented.
A vertex detector for the International Linear Collider based on CMOS sensors
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2006
The physics programme at the International Linear Collider (ILC) calls for a Vertex Detector (VD) providing unprecedented flavour tagging performances, especially for c-quarks and τ leptons. This requirement makes a very granular, thin and multilayer vertex detector installed very close to the interaction region mandatory. Additional constraints, mainly on read-out speed and radiation tolerance, originate from the beam background, which governs the occupancy and the radiation level the detector should be able to cope with. CMOS sensors are being developed to fulfil these requirements. This report addresses the ILC requirements (highly related to beamstrahlung), the main advantages and features of CMOS sensors, the demonstrated performances and the specific aspects of a vertex detector based on this technology. The status of the main R&D directions (radiation tolerance, thinning procedure and read-out speed) are also presented.
IEEE Transactions on Nuclear Science, 2000
3D-Integrated Circuit technology enables higher densities of electronic circuitry per unit area without the use of nanoscale processes. It is advantageous for mixed mode design with precise analog circuitry because processes with conservative feature sizes typically present lower process dispersions and tolerate higher power supply voltages, resulting in larger separation of a signal from the noise floor. Heterogeneous wafers (different foundries or different process families) may be combined with some 3D integration methods, leading to the optimization of each tier in the 3D stack. Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20×20 μm 2 pixels, laid out in an array of 64×64 elements and was fabricated in a 3-tier 0.18 μm Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout. Successive submissions are planned in a commercial 3D bulk 0.13 μm CMOS process to overcome some of the disadvantages of an FDSOI process.
2005
CMOS sensors are being developed to equip a vertex detector offering the perfomances required for the physics programme at the International Linear Collider. The progress realised from Spring 2003 to Spring 2005 is exposed in this report. It addresses the exploration of new fabrication processes, the design of fast integrated signal processing micro-circuits, the assessment and improvement of the radiation tolerance, the reduction of the power dissipation, the thinning of the sensors, the design of a light mechanical support and cooling studies. Progresses were also achieved on a detector design exploiting the features of CMOS sensors. Since several performance requirements are dictated by the beamstrahlung electron rate, the latter was revisited and assessed with improved accuracy. The constraints coming out from this study are significantly more stringent than those written in the TESLA TDR.
2021
CMOS sensors were successfully implemented in the STAR tracker [1]. LHC experiments have shown that efficient b tagging, reconstruction of displaced vertices and identification of disappearing tracks are necessary. An improved vertex detector is justified for the ILC. To achieve a point(spatial single layer) resolution below the one-{\mu}m range while improving other characteristics (radiation tolerance and eventually time resolution) we will need the use of 1-micron pitch pixels. Therefore, we propose a single MOS transistor that acts as an amplifying device and a detector with a buried charge-collecting gate. Device simulations both classical and quantum, have led to the proposed DoTPiX structure. With the evolution of silicon processes, well below 100 nm line feature, this pixel should be feasible. We will present this pixel detector and the present status of its development in both our institution (IRFU) and in other collaborating labs (CNRS/C2N).
Development of the Continuous Acquisition Pixel (CAP) sensor for high luminosity lepton colliders
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2006
A future higher luminosity B-factory detector and concept study detectors for the planned International Linear Collider require precision vertex reconstruction while coping with high track densities and radiation exposures. Compared with current silicon strip and hybrid pixels, a significant reduction in the overall detector material thickness is needed to achieve the desired vertex resolution. Considerable progress in the development of thin CMOS-based Monolithic Active Pixel Sensors (MAPS) in recent years makes them a viable technology option and feasibility studies are being actively pursued. The most serious concerns are their radiation hardness and their readout speed. To address these, several prototypes denoted as the Continuous Acquisition Pixel (CAP) sensors have been developed and tested. The latest of the CAP sensor prototypes is CAP3, designed in the TSMC 0.25µm process with a 5-deep Correlated Double Sample (CDS) pair pipeline in each pixel. A setup with several CAP3 sensors is under evaluation to assess the performance of a full scale pixel read-out system running at realistic read-out speed. Given the similarity in the occupancy numbers and hit throughput requirements, per unit area, between a Belle vertex detector upgrade and the requirements for a future ILC pixel detector, this effort can be considered a small-scale functioning prototype for such a future system.
Pixel detectors in 3D technologies for high energy physics
2010 IEEE International 3D Systems Integration Conference (3DIC), 2010
This paper reports on the current status of the development of International Linear Collider vertex detector pixel readout chips based on multi-tier vertically integrated electronics. Initial testing results of the VIP2a prototype are presented. The chip is the second embodiment of the prototype data-pushed readout concept developed at Fermilab. The device was fabricated in the MIT-LL 0.15 µm fully depleted SOI process. The prototype is a three-tier design, featuring 30×30 µm 2 pixels, laid out in an array of 48×48 pixels.
Development of a prototype module for a DEPFET pixel vertex detector for a linear collider
IEEE Transactions on Nuclear Science, 2000
For operation at a linear collider the excellent noise performance of DEPFET pixels allows building very thin detectors with high spatial resolution and low power consumption. However, high readout speeds of 50 MHz line rate and 20 kHz for the full detector must be reached. A prototype system is presented, using a new DEPFET pixel matrix (128 x 64 pixels), fast steering chips (Switcher II) for row wise operation and a fast current based readout chip (CURO II). The sensors with small linear DEPFET pixels (22 x 36 µm 2 ) are optimized for fast readout and high spatial resolution. Measurements show that the complete removal of the accumulated signal charge from the internal gate (complete clear), which is fundamental for the foreseen readout mode, is feasible. The current based readout chip CURO II, containing current memory cells, pedestal subtraction and on chip zero suppression for a triggerless operation has been fabricated and tested. First results of a full prototype system are presented.