Modeling C–V characteristics of deep sub-0.1 micron mesoscale MOS devices (original) (raw)
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Solid-State Electronics, 2004
A new solution to account for the quantum mechanical effects (QME) in an explicit surface-potential-based MOSFET model is presented. The inclusion of QME is achieved using a variational approach to the solution of the Schr€ o odinger and Poisson equations. The resulting physics-based model is fully analytical and suitable for the simulation of deep-submicron MOSFETs, with highly doped substrates and ultra-thin gate oxide thicknesses. It gives an accurate and continuous description of the surface potential and its derivatives from depletion to strong inversion region. An important point is that the model is developed for a MOSFET device, and not only for a MOS capacitor, so it is fully dependent on all terminal voltages. The quantum explicit surface potential model leads to excellent results in comparison with full QM self-consistent calculations (coupled Schr€ o odinger-Poisson simulations) for a large range of substrate doping and oxide thickness. Comparisons with experimental data from various deep-submicron CMOS technologies show accurate fits for both I-V and C-V characteristics.
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By applying a fully self-consistent solution of the Schrödinger-Poisson equations, a simple unified approach has been developed in order to study the gate current and gate capacitance of nanoscale-MOS structures with ultrathin dielectric layer. In this paper, the model has been employed to investigate various gate structure and material combinations, thereby demonstrating wide applicability of the present model in the design of nanoscale-MOSFET devices. The results obtained by applying the proposed model are in good agreement with experimental data and previous models in the literature. A new result concerning optimum nitrogen content in HfSiON high-k gate-dielectric structure reported in this paper requires experimental verification through device fabrication.
Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics
Solid-State Electronics, 2004
Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region.
IEEE Transactions on Electron Devices, 2005
A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schrödinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations 1 2 3 ox , often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (-) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO 2 , Si 3 N 4 and high-(e.g., HfO 2) gate dielectrics on (100) Si with EOTs down to 1 3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance. Index Terms-Compact gate capacitance-voltage (-) modeling, Fermi-Dirac statistics, interface states, quantum-mechanical (QM) effects, wave function penetration. I. INTRODUCTION A S THE aggressive scaling of CMOS technology continues, the equivalent physical oxide thickness (EOT) of gate dielectrics is projected by the International Technology Roadmap for Semiconductors (ITRS 2003 Edition) to become as thin as 0.5 nm in some cases in the next 15 years [1]. To overcome the well-known increasingly serious technology difficulties of Manuscript
An explicit surface-potential-based MOSFET model incorporating the quantum mechanical effects
Solid-state Electronics, 2006
An explicit surface-potential-based MOSFET model has been proposed in this work here, which takes into account the quantum mechanical effects that arise in deep-submicron MOSFETs. The coupled Schrö dinger's and Poisson's equations have been solved by using a variational wave function approach, as proposed by Fang and Howard. The resulting surface potential model is analytical, technology mapped, and completely continuous over the entire range of operation. The surface potential and the inversion charge density calculated using the proposed model show good match with the results of the numerical simulations obtained from a self-consistent Schrö dinger-Poisson solver for a wide range of substrate doping and oxide thickness. The simulated values of the drain current match closely with the experimental results published elsewhere. The device small-signal parameters, e.g., transconductance, output conductance, etc., pass the standard benchmark tests suggested by Suyama and Tsividis qualitatively, thereby validating the approach of the model presented.
Quantum Potential Approach to Modeling Nanoscale MOSFETs
Journal of Computational Electronics, 2005
We propose a novel parameter-free quantum potential scheme for use in conjunction with particlebased simulations. The method is based on a perturbation theory around thermodynamic equilibrium and leads to an effective potential scheme in which the size of the electron depends upon its energy. The approach has been tested on the example of a MOS-capacitor by retrieving the correct sheet electron density. It has also been used in simulations of a 25 nm n-channel nanoscale MOSFET with high substrate doping density. We find that the use of the quantum potential approach gives rise to a threshold voltage shift of about 220 mV and drain current degradation of about 30%.
IEEE Transactions on Electron Devices, 2007
A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO 2 , HfO 2 , and SiO 2 gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V th. This effect is also observed in the variance of V th , due to dopant fluctuation under the gate.
A SPICE-compatible model for nanoscale MOSFET capacitor simulation under the inversion condition
IEEE Transactions On Nanotechnology, 2002
A SPICE-compatible charge model for nanoscale MOSFETs is proposed. Based on the solution of Schrödinger-Poisson (S-P) equations, the developed compact charge model is optimized with respect to: 1) the position of the charge concentration peak; 2) the maximum of the charge concentration; 3) the total inversion charge sheet density; and 4) the average inversion charge depth, respectively. This model can predict inversion layer electron density for various oxide thicknesses and applied voltages. Compared to the S-P results, our model prediction is within 5% of accuracy. Application of this charge quantization model to the C-V measurement produces an excellent agreement. This compact model has continuous derivatives and is therefore amenable to a device simulator. It can also be easily incorporated into circuit simulator for modeling ultrathin oxide MOSFET C-V characteristics.
Efficient MultiDimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices
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We investigate the density-gradient (DG) transport model for efficient multi-dimensional sim- ulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction to the classical drift-diffusion model. Quantum con- finement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capaci- tors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum con- finement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-grad...
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We present a thermodynamic approach to introducing quantum corrections to the classical transport picture in semiconductor device simulation. This approach leads to a modified Boltzmann equation with an effective quantum potential. We study the quantum interaction of electrons with a gate oxide barrier potential in a 25 nm MOSFET.