Power Optimised Digital Filterbank as Part of a Psychoacoustic Human Hearing Model (original) (raw)

Low power system on chip implementation scheme of digital filtering cores

The paper describes a scheme for the implementation of low power cores for hearing aid applications. Power saving features of the scheme are two fold. The first due to the utilisation of a macro-component framework which allows the rapid assembly of the cores on easy-to-verify hierarchical plug-in basis. The second is due to the system-on-chip strategy. The cores are embedded within an ARM-based system-on-chip platform. For this VSIA compliant wrapper interfaces have been investigated which allow the cores operation in multiple clock and bus domains. This provides effective power manipulation by power management strategies. The paper demonstrates the scheme with a number of FIR filtering cores. The cores are assembled with a number of different macro-components from the wide range available within a rich library which contains a flexible and synthesisable set of components for computation, memory, decision, and BIST functions.

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

Proceedings of the 43rd annual conference on Design automation - DAC '06, 2006

This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60 mW in a 0.25 µm CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42 mW) and the isomorphic architecture (1.54 mW), without overly large area overhead (0.77 mm 2 against 0.43 mm 2 and 4.31 mm 2 , respectively).

Anawake: Signal-Based Power Management For Digital Signal Processing Systems

2007

Single-chip, low-power, programmable digital signal processing systems are capable of hosting complete speech processing applications, while consuming a few milliwatts of average power. We present a power management architecture that decreases the average power consumption of these systems to 3-10 microwatts, in applications where speech signals are present with a sufficiently low duty cycle. In this architecture, a micropower analog signal processing system, Anawake, continuously analyzes the incoming signal, and controls the power consumption of the DSP system in a signal-dependent way. We estimate system power consumption for Anawake designs optimized for different peak-speech-signal to average-background-noise ratios.

Power Consumption in Novel Digital Filters

This paper describes an investigation into the power consumption of a Finite Impulse Response (FIR) filter, designed using primitive operator arithmetic (POF). The filter was compared with a standard FIR filter created using conventionally structured multiplier blocks. The filters were created using Matlab and VHDL coding techniques. In order to maintain control of the structural implementations, both filters were created using only structural modeling methods. Power consumption estimations were made using Xilinx’s XPower software which indicated a possible 34% saving in dynamic power consumption, and a possible 2.5% saving in total power consumption in favour of the POF filter structure.

An Optimum Inexact Design for an Energy Efficient Hearing Aid

Journal of Low Power Electronics, 2019

Inexact design has proved to be an efficient way of obtaining power savings with a marginal penalty on performance in applications which do not need high degree of output accuracy. Such applications are often found in domains which deal with human sensorial systems. The 'not so perfect' state of human senses like sight, hearing which are important for video and audio related appliances can compensate for the error introduced due to inexact design. An efficient analysis and modelling of these compensation capabilities of human senses can help the designers to build optimum inexact architectures meeting the redefined requirements with low power. In this work, we choose hearing aid as our test application, which is based on human sense of hearing. We estimate a metric Intelligibility, for a set of audio samples, which is obtained from multiple surveys on human subjects to model the sensorial processing. Our methodology uses a novel way of introducing inexactness in an optimum manner. This includes a fine grained analysis of the error that is being introduced in the FIR filters of the DSP present in hearing aid. The resulting inexact FIR filter bank is 1.92× or 2.56× more efficient in terms of power consumed while producing 10% or 20% less intelligible speech respectively when compared with a hearing-aid using exact filters.

Low Power Adder Based Auditory Filter Architecture

The Scientific World Journal, 2014

Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

Battery-Friendly Design of Signal Processing Algorithms

Signal Processing Systems, …, 2003

Portable systems today are designed with lowering the energy consumption as the primary design metric. This is unfortunate since maximizing battery lifetime is a more appropriate inetric, and lowering energy does not necessarily mean improving battery lifetime. In this paper we ...

Low-Power Digital Signal Processor Design for a Hearing Aid

A new low-power digital signal processor (DSP) design for a hearing aid system is proposed. A stochastic method was applied to the DSP in order to fulfill the needs of the hearing aid system, considered to be an error-tolerant system. The different blocks that form the DSP are presented in this paper. The implementation and layout were performed and simulated using a 90 nm CMOS process. Simulation results showed excellent energy consumption savings in the range of 4.5x to 10x of the proposed DSP design when compared to similar DSPs.

Architectural trade-offs in the design of low power FIR filtering cores

Iee Proceedings-circuits Devices and Systems, 2004

There is a continuous drive for methodologies and approaches of low power design. This is mainly driven by the surge in portable computing. On the other hand, the design of low power systems for different portable applications is not a simple task. This is because of the number of constraints that influence the power consumption of a device. In addition to issues of performance and functionality, there is a need to satisfy strict test coverage constraints. The authors investigate the impact of DSP architectural realisation, multiplier type, and the choice of number representation on the overall power consumption of DSP devices. Work in the literature so far has concentrated on the effect of these on a part or a section of a DSP system. Furthermore the effect of DfT circuits on the overall performance is studied. A hearing aid device is considered as an example of a system with strict power/area constraints. It is shown that the choice of multiplier architecture and number representation should be carefully considered when specific DSP architectural choices are made. The results are demonstrated with a number of specially designed DSP architectures for the implementation of FIR filtering algorithms on hearing aid devices.

Power-Aware Acoustic Processing

Lecture Notes in Computer Science, 2003

We investigated the tradeoffs between accuracy and battery-energy longevity of acoustic beamforming on disposable sensor nodes subject to varying key parameters: 1) number of microphones, 2) duration of sampling, 3) number of search angles, and 4) CPU clock speed. Beyond finding the most energy efficient implementation of the beamforming algorithm at a specified accuracy, we seek to enable application-level selection of accuracy based on the energy required to achieve this accuracy. Our energy measurements were taken on the HiDRA node, provided by Rockwell Science Center, employing a 133-MHz StrongARM processor. We compared the accuracy and energy of our time-domain beamformer to a Fourier-domain algorithm provided by the Army Research Laboratory (ARL). With statistically identical accuracy, we measured a 300x improvement in energy efficiency of the CPU relative to this baseline. We also present other algorithms under development that combine results from multiple nodes to provide more accurate line-of-bearing estimates despite wind and target elevation.