Synthesis and characterization of low-k films for large area imaging applications (original) (raw)
Related papers
Study of capacitance in hydrogenated amorphous silicon phototransistors for imaging arrays
Journal of Non-Crystalline Solids, 2004
In this paper we report on the study of capacitance in hydrogenated amorphous silicon phototransistors in order to determine their applicability in large area imaging systems. Measured capacitance values exceed the geometrical one at low frequencies of the probe signal, both in the dark and under illumination. In particular, capacitance values in excess of 60 lF/cm 2 are measured under 220 lW/cm 2 illumination at 600 nm. The experimental data have been reproduced by a numerical device simulator, which takes into account the distribution of defects in amorphous materials. We have found that capacitance is mainly determined by the trapping and release processes occurring in the base and at the interfaces between the intrinsic and the n-layers of the device. At these interfaces, the Fermi level lies in correspondence with the band tails, whose high number of defects causes a large variation of trapped charge in response to the a.c. applied voltage.
Integration issues for polymeric dielectrics in large area electronics [TFTs]
2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595), 2002
The issues concerning the integration of polymeric low-permittivity (low-k) dielectrics in amorphous Si (a-Si) thin-film transistor (TFT) arrays have been investigated. A photosensitive spin-on polymer, Photo-Benzocyclobutene (PBCB), has been studied for integration as interlevel dielectric between the transistor and pixel levels in TFT arrays. The dielectric films were characterized by permittivity, stress, and planarization measurements. The dielectric constant was found to be in the range of 2.5-3.5. The degree of planarization was >90%, and the film stress was about 60 MPa. Process parameters have been optimized for integration in TFT arrays. Measurements on test structures showed low leakage current and good electrical contact at via interconnections.
Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates
MRS Proceedings, 1999
ABSTRACTThe fabrication of large-area thin-film transistor (TFT) arrays on thin flexible plastic substrates requires deposition of thin film layers at relatively low temperatures since the upper working temperature of low-cost plastic films should not exceed ∼200°C. In this paper, we report a fabrication process of a-Si:H TFTs at 120°C on flexible polyimide substrates for large-area imaging applications.Kapton HN (DuPont) films 50 and 125 μm thick and 3 inches in diameter, were used as substrates. Both sides of the polyimide substrate were first covered with 0.5 μm thick a-SiNx. The TFT structure includes: 120 nm thick room-temperature sputtered Al gate, 250 nm thick PECVD deposited a-SiNx for the gate dielectric, 50 nm thick a-Si:H deposited by PECVD from silane-hydrogen gas mixture, 50 nm thick n+ a-Si:H source- and drain contacts, and roomtemperature sputtered Al top contact metallization. We used dry etching for all layers except for the gate and top metal, which were patterned ...
physica status solidi (RRL) – Rapid Research Letters, 2011
This study investigates the correlation between surface energy of polymer dielectrics and the film morphology, microstructure, and thin‐film transistor performance of solution‐processed 5,11‐bis(triethylsilylethynyl) anthradithiophene (TES‐ADT) films. The low surface energy polyimide (PI) dielectric induced large grains with strong X‐ray reflections for spin‐cast TES‐ADT films in comparison to high surface en‐ ergy poly(4‐vinyl phenol) (PVP) dielectric. Furthermore, thin‐film transistors based on spin‐cast TES‐ADT films on PI dielectric exhibited enhanced electrical performance, small hysteresis, and high stability under bias stress with carrier mobility as high as 0.43 cm2/Vs and a current on/off ratio of 107. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)
Low-Temperature Materials and Thin Film Transistors for Flexible Electronics
Proceedings of the IEEE, 2000
This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a 0 SiN x ) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75 C and 120 C. The a-Si:H TFTs fabricated at 120 C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (FE) of 0.8 cm 2 V 01 s 01 , the threshold voltage (VT) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75 C exhibit FE of 0.6 cm 2 V 01 s 01 , and VT of 4 V. It is shown that further improvement in TFT performance can be achieved by using n + nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.
Journal of Non-Crystalline Solids, 2002
In this paper we present results concerning the optimisation of the electronic and mechanical properties presented by amorphous silicon (a-Si:H) thin films produced on polyimide (Kapton â VN) substrates with different thicknesses (25, 50 and 75 lm) by the plasma enhanced chemical vapour deposition (PECVD) technique. The purpose of this study is to obtain a low defect density as well as low residual stresses (specially at the interface) in order to provide good performances for large area (10 mm wide by 80 mm long) flexible position sensitive detectors. The electrical and optical properties presented by the films will be correlated to the sensor characteristics. The properties of samples have been measured by dark/photoconductivity, constant photocurrent measurements (CPM) and the results have been compared with films deposited on Corning 7059 glass substrates during the same run deposition. The residual stresses were measured using an active optical triangulation and angle resolved scattering. The preliminary results indicate that the thinner polymeric substrate with 25 lm presents the highest density of states, which is associated to the residual stresses and strains associated within the film. Ó
High-resolution high fill factor a-Si:H sensor arrays for medical imaging
Medical Imaging 1999: Physics of Medical Imaging, 1999
Amorphous silicon large area sensor arrays are in production for x-ray medical imaging. The most common pixel design works very well for many applications but is limited in spatial resolution because the available sensor area (the fill factor) vanishes in small pixels. One solution is a 3-dimensional structure in which the sensor is placed above the active matrix addressing. However, such high fill factor designs have previously introduce cross talk between pixels. We present data for a design in which the a-Si:H p-in photodiode sensor layer has a continuous i-layer and top pt-layer, and a patterned ne-layer contact to the pixel. Arrays of 64 gim and 75[tm pitch have been fabricated and are the highest resolution a-Si:H arrays reported to date. The resolution matches the pixel size, and sensitivity has been improved by the high fill factor. Comparison is made between arrays with standard TFTs and TFTs with self-aligned source and drain contacts. Data line capacitance is improved by use of the self-aligned contacts. Measurements are included on the contact to bias capacitance. The high fill factor design greatly suppresses lateral leakage currents, while retaining ease of processing. Provided illumination levels remain below saturation, the resolution matches expectation for the pixel size.
High performance amorphous silicon image sensor arrays
Journal of Non-Crystalline Solids, 1998
. We discuss approaches to improve the performance of amorphous silicon a-Si X-ray imagers. Imager size has been increased to 30 = 40 cm and the number of pixels to ) 7 million. Processing improvements have nearly doubled the sensor Ž . fill factor and hence sensitivity and have reduced the data line capacitance which is the principal contribution to the Ž . electronic noise of the system. With new thin film transition TFT technology both amorphous and polysilicon TFTs made with the identical structure, using laser recrystallization are produced. The hybrid approach allows smaller leakage current a-Si:H devices to be used for the pixel TFT, and high mobility polysilicon devices for peripheral electronics. Arrays incorporating a lead iodide X-ray photoconductor have promise for higher sensitivity provided the leakage current can be reduced. q