Design tools for reconfigurable embedded systems (original) (raw)

Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer

2005

We report on work-in-progress that aims to provide a run-time management kernel for applications running on FPGAs with embedded CPUs. We describe the global con-cept, the organization of the hardware environment for the reconfigurable modules and the reconfiguration strategy supported by the run-time management kernel. Practical issues concerning the implementation of the system on a Virtex-II Pro-based board are also addressed. 1.

A Run-Time System for Partially Reconfigurable FPGAs: The case of

2016

During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM pro-cessor alongside with a Virtex-5 FPGA daughter-board. While partial reconfigura-tion in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The pa-per discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogu...

A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board

2015

During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM processor alongside with a Virtex-5 FPGA daughter-board. While partial reconfiguration in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The paper discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogurab...