Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors (original) (raw)
Related papers
1999
Time±resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler±Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n + poly-crystalline Si/SiO 2 /n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques. 7
J Appl Phys, 1999
We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers with thickness between 35 and 5.6 nm in n+ polycrystalline Si-SiO2-Si metal/oxide/semiconductor capacitors after constant voltage Fowler-Nordheim stress. The buildup of defects in the oxide during the degradation phase was monitored by quasi static C-V measurements. The dynamics of the final breakdown event was followed with high time resolution, allowing to measure voltage, current, and power versus time during the breakdown transient. Transmission electron microscopy data quantifying the damage produced during this transient are reported. Finally, we propose a phenomenological model concerning the dynamics of breakdown with model parameters adjusted on the basis of the experimental data.
Journal of Applied Physics, 1999
We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers with thickness between 35 and 5.6 nm in n ϩ polycrystalline Si-SiO 2 -Si metal/oxide/semiconductor capacitors after constant voltage Fowler-Nordheim stress. The buildup of defects in the oxide during the degradation phase was monitored by quasi static C-V measurements. The dynamics of the final breakdown event was followed with high time resolution, allowing to measure voltage, current, and power versus time during the breakdown transient. Transmission electron microscopy data quantifying the damage produced during this transient are reported. Finally, we propose a phenomenological model concerning the dynamics of breakdown with model parameters adjusted on the basis of the experimental data.
Soft breakdown of gate oxides in metal–SiO[sub 2]–Si capacitors under stress with hot electrons
Applied Physics Letters, 1999
We have investigated the intrinsic dielectric breakdown of gate oxide layers with thickness of 12 and 7 nm in n ϩ polycrystalline Si-SiO 2 -Si metal/oxide/semiconductor ͑MOS͒ capacitors after stress with constant current either under Fowler-Nordheim or under hot electron injection. Occurrence of soft breakdown without thermal damage in the MOS structure is demonstrated even in a 12 nm oxide under particular stress conditions. In general, it is found that the type of stress determines the breakdown mode ͑soft or hard͒.
Journal of Applied Physics, 1998
The dielectric breakdown of gate oxide layers with thickness of 35 and 9.3 nm in metal-oxide-semiconductor capacitors with a n ϩ polycrystalline Si/SiO 2 /n Ϫ Si stack was investigated. Breakdown was characterized in a particular circuit configuration by following the time evolution of voltage, current, and power through the capacitor with a time resolution of the order of 2 ns. A detailed morphological characterization of the damaged samples by emission and transmission electron microscopy is shown and discussed. The results of the morphological analysis and of the electrical measurements are quantitatively discussed by simulating, through heat-flow calculations, the time evolution of the temperature in the regions interested to the breakdown phenomenon.
Dielectric breakdown mechanisms in gate oxides
Journal of Applied Physics, 2005
In this paper we review the subject of oxide breakdown ͑BD͒, focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1 nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during which the gate leakage increases above acceptable levels. In conditions of intrinsic BD, the leakage increase is due to the growth of damage within the oxide in localized regions. Observations concerning this damage are reviewed and discussed. The measurement of the current, voltage, and power dissipated during the BD transient are also reported and discussed in comparison with the data of structural damage. We then describe the current understanding concerning the dependence of the BD current transient on the conditions of electric field and voltage. In particular, as the oxide thickness and, as a consequence, the voltage levels used for accelerated reliability tests have decreased, the BD transient exhibits a marked change in behavior. As the stress voltage is decreased below a threshold value, the BD transient becomes slower. This recently discovered phenomenon has been termed progressive BD, i.e., a gradual growth of the BD spot and of the gate leakage, with a time scale that under operation conditions can be a large fraction of the total time to BD. We review the literature on this phenomenon, describing the current understanding concerning the dependence of the effect on voltage, temperature, oxide thickness, sample geometry, and its physical structure. We also discuss the possible relation to the so-called soft oxide BD mode and propose a simpler, more consistent terminology to describe different BD regimes. The last part of the paper is dedicated to exploratory studies, still at the early stages given the very recent subject, concerning the impact on the BD of materials for the metal-oxide-semiconductor gate stack and, in particular, metal gates.
Charge Build up and Breakdown in Thin Sio2 Gate Dielectrics
IEEE Transactions on Electrical Insulation, 1984
SiO2 layers with low defect densities have been grown in a double-walled oxidation tube, for use as thin gate dielectrics in MOS IC's. Under all highfield stress conditions positively charged slow states are created at the Si-SiO2 interface. These can be neutralized by applying positive fields at the gate of an MOS device. Negative charge can also be generated, especially during a positive field stress. The total amount of generated charge is much less for polysilicon gate capacitors than for Al-gate capacitors. The time-to-breakdown in a wearout experiment could be extended by periodic application of a positive gate voltage. This also caused neutralization of the slow states. However, it had no influence on the high-field breakdown distribution in a fast voltage ramp experiment. It is suggested that interface rather than bulk phenomena dominate trap generation and charge build-up during the high-field stresses which induce oxide breakdown.
Intrinsic dielectric breakdown of ultra-thin gate oxides
Microelectronic Engineering, 2001
We have investigated the dynamics of intrinsic dielectric breakdown (BD) in SiO thin films of thickness in the range 2 from 35 to 3 nm. BD is obtained under constant voltage Fowler-Nordheim stress at fields between 10 and 12.5 MV/ cm. As a function of oxide thickness we have followed with high time resolution the dynamics of the BD transient and analysed the post-BD damage by using transmission electron microscopy, photon emission microscopy and measurements of the post-BD current-voltage (I-V) characteristics. Moreover, the effect of the density of electrons at the cathode on the resulting BD damage is put in evidence. The data are interpreted and discussed in the framework of a model.
Degradation and Breakdown of Gate Oxides in VLSI Devices
Physica Status Solidi (a), 1989
Degradation and Breakdown of Gate Oxides in VLSI Devices BY J. SURE, I. PLACENCIA, N. BARNIOL, E. FARRES, and X. AYMERICH A model for the degradation and breakdown of thin gate oxide films is presented. During electrical stresses, a small fraction of the energy of the tunnel electrons that is dissipated in the oxide is converted into the creation of electron traps. When a critical density of traps is achieved, a fast runaway process leads the oxide t o break down and its insulating properties are irreversively lost. It is demonstrated that the total charge injected to breakdown depends on the applied current in accordance with recently published results. The quasi-linear log (time-to-breakdown) versus log (current density) plot experimentally obtained for VLXI oxides (tax = 100 A) is correctly predicted. Un model pour expliquer la degradation et la rupture des couches minces de SiO, en structures MOS est present& Une petite fraction de l'energie des Blectrons tunnel dissipee dans la couche d'oxyde pendant le stress Blectrique de la structure est employee en la creation de pikges d'6lectrons. Quand on arrive A une certaine densite critique de centres Blectroniques g6nBrBs, un mechanisme de runaway produit tres rapidement la rupture. Nous avons explique theoriquement la dependence experimentelle de la charge injectke jusqu'i la rupture avec le courant appliquk. La relation quasi-IinBaire entre log (temps de rupture) et log (dBnsit6 de courant) qu'on trouve experimentellement a i.t6 correctement prbdite. 1) E-08 193 Bellaterra, Spain.
Reduction of thermal damage in ultrathin gate oxides after intrinsic dielectric breakdown
Applied Physics Letters, 2001
We have compared the thermal damage in ultrathin gate SiO 2 layers of 5.6 and 3 nm thickness after intrinsic dielectric breakdown due to constant voltage Fowler-Nordheim stress. The power dissipated through the metal-oxide-semiconductor capacitor during the breakdown transient, measured with high time resolution, strongly decreases with oxide thickness. This is reflected in a noticeable reduction of the thermal damage found in the structure after breakdown. The effect can be explained as the consequence of the lower amount of defects present in the oxide at the breakdown instant and of the occurrence of a softer breakdown in the initial spot. The present data allow us to estimate the power threshold at the boundary between soft and hard breakdown, and they are compared to numerical simulations of heat flow.