FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m) (original) (raw)

An FPGA implementation of an elliptic curve processor GF(2 ^m )

2004

This paper describes a hardware implementation of an arithmetic processor which is efficient for elliptic curve (EC) cryptosystems, which are becoming increasingly popular as an alternative for public key cryptosystems based on factoring. The modular multiplication is implemented using a Montgomery modular multiplication in a systolic array architecture, which has the advantage that the clock frequency becomes independent of the bit length m.

An FPGA implementation of an elliptic curve processor GF (2 m)

Proceedings of the 14th ACM Great …, 2004

Fpga Implementations of High Speed Elliptic Curve Cryptography: A Survey

ijser.org

An explosi ve acceptance of Elliptic Curve Cryptography (ECC) has been attained in the industry and academics. Elliptic Curve cryptography i s an approach to public-key cryptography based on the algebrai c structure of elliptic curves over finite fields. The ECC is advantageous due to the provision of high level of security and the usage of small keys. In the field of Mobile, Wireless and Network servers, to sustain the high throughput the implementations of high speed crypto-systems are needed. ECC has been extensivel y used for hardware implementation of FPGA and DedicatedASIC. This paper attempts to conduct a detailed survey on di fferent techniques for implementing FPGA using ECC to achieve high speed and flexibility.

Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA

Mathematical Problems in Engineering, 2013

The high performance of an elliptic curve (EC) crypto system depends efficiently on the arithmetic in the underlying finite field. We have to propose and compare three levels of Galois Field GF(2 163), GF(2 193), and GF(2 256). The proposed architecture is based on Lopez-Dahab elliptic curve point multiplication algorithm, which uses Gaussian normal basis for GF(2 163) field arithmetic. The proposed GF(2 193) is based on an efficient Montgomery add and double algorithm, also the Karatsuba-Ofman multiplier and Itoh-Tsujii algorithm are used as the inverse component. The hardware design is based on optimized finite state machine (FSM), with a single cycle 193 bits multiplier, field adder, and field squarer. The another proposed architecture GF(2 256) is based on applications for which compactness is more important than speed. The FPGA's dedicated multipliers and carry-chain logic are used to obtain the small data path. The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication, increases frequency and the speed of operation such as key generation, encryption, and decryption. Finally, we have to implement our design using Xilinx XC4VLX200 FPGA device.

On the hardware design of an elliptic curve cryptosystem

Proceedings of the Fifth Mexican International Conference in Computer Science, 2004. ENC 2004., 2004

We present a hardware architecture for an Elliptic Curve Cryptography System performing the three basic cryptographic schemes: DH key generation, encryption and digital signature. The architecture is described by using hardware description languages, specifically Handel C and VHDL. Because of the sequential nature of the cryptographic algorithms, they are written in Handel C language. The critical part of the cryptosystem is a module performing the scalar multiplication operation. This module has been written in VHDL to let further improvements. The points of the elliptic curve are represented in projective coordinates working over the two-characteristic finite field and using polynomial basis. A prototype of this hardware architecture is implemented on a Xilinx Virtex II FPGA device.

FPGA based hardware acceleration for elliptic curve public key cryptosystems

Journal of Systems and Software, 2004

trations (E-Government) give rise to the important question, how to reliably exchange confidential data via public communication networks such as the Internet. Any data transfer must be protected from a fraudulent access by third parties in the sense that it has to be ensured that exchanged documents are neither read nor modified during the data transfer. Furthermore, the author-document relationships have to be known and unique at any point in time. The fundamental technology for document protection during public data transfer is known as public key cryptography. Digital signature schemes are probably the most common occurrence of public key cryptosystems. This paper addresses public key cryptosystems based on elliptic curves, which are aimed to high-performance digital signature schemes. Elliptic curve (EC) algorithms are characterized by the fact that one can work with considerably shorter keys compared to the RSA approach at the same level of security. A general and highly efficient method for mapping the most time-critical operations to a configurable co-processor is proposed. By means of real-time measurements the resulting performance values are compared to previously published state of the art hardware im-

Efficient FPGA elliptic curve cryptographic processor over GF(2^m)

2008 International Conference on Field-Programmable Technology, 2008

In this paper a processor that supports elliptic curve cryptographic applications over GF (2 m ) is proposed. The proposed structure is capable of calculating point multiplication and addition using a single coordinate to contain the point information. This compression allows for a better usage of the bandwidth resources. For the point multiplication procedure, all coordinate pre-calculations are completely avoided. This design was successful prototyped on a reconfigurable device for the field GF (2 163 ). Experimental results suggest that point multiplication can be performed in 144μs and point affine addition in 1.02μs. Comparing with the related work, a 5 times speedup is obtained for point addition and multiplication. The presented design offers a well balanced area-time performance when compared with existent elliptic curve point multiplication specific processors.

Customizable elliptic curve cryptosystems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2 ), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple -bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.

Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

International Journal of Network Security & Its Applications, 2010

In this paper, we propose an elliptic curve key generation processor over GF scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis. The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the high efficiently of this implementation design.

FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m) (original) (raw)

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