Robust bias temperature instability refresh design and methodology for memory cell recovery (original) (raw)
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Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Proceedings of the …, 2011
Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level.
Impact of NBTI on SRAM Read Stability and Design for Reliability
Proceedings of the 7th …, 2006
Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.
IEICE Transactions on Electronics, 2014
This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and onchip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V dd and it provides 91 times better failure rate with a 35% droop of V dd compared with the conventional design.
Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems
2010
There are wide power variations across a chip leading to temperature variations. High power density components such as register files and arithmetic logic units will trend towards elevated temperatures while other lower power density units will be cooler. Higher temperatures in general decrease the lifetime reliability of digital systems through a number of mechanisms. Furthermore, continued scaling leads to an increase in soft error occurrences. To this end in addition to increasing the error resiliency of register files a proposal that would also lower energy per access is presented. The power modes available to save power also have the effect of lowering the rate of certain degradation. The effect of negative bias temperature instability (NBTI) on SRAM cells under power saving modes is investigated for leakage current, read and hold margins. This is done for both symmetric and asymmetric cells. Noting that temperature variations occurs across a chip, we present techniques to lowe...
A Faster Approach to Periodic Data Flipping of SRAM Array for NBTI Recovery
—Negative Bias Temperature Instability (NBTI) is a prime reliability issue for micro and nano-scale semiconductor devices. Due to continuous device scaling, NBTI effect has become more severe than before and affected device lifetime. Memory devices like SRAMs are tremendously affected by NBTI as the PMOS transistor gate is connected at '0' logic for a long time. Several device-level and architecture-level solutions have been proposed to improve device lifetime by interrupting NBTI degradation. Such an architectural level solution is to flip data in a particular SRAM cell after a certain time, causing periodic stress and relaxation. SRAM data flipping techniques proposed so far are not so time friendly as it is needed to access each memory cell individually and flip the data stored. It makes the process more time consuming and inconvenient for present ultra-fast system with high activity factor. In this paper, we proposed a new 7-T SRAM cell to allow flipping data of more than one memory cells at same clock pulse, hence decreasing the flipping time of entire memory array and concluded that with the new proposed cell and flipping procedure, data flipping of the entire memory array will become much faster which will ensure convenient NBTI recovery.
Impact of negative and positive bias temperature stress on 6T-SRAM cells
Advances in Radio Science, 2009
With introduction of high-k gate oxide materials, the degradation effect Positive Bias Temperature Instability (PBTI) is starting to play an important role. Together with the still effective Negative Bias Temperature Instability (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event.
Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis
IEEE Transactions on Device and Materials Reliability
Abstract-This paper presents two different topologies of 11T SRAM cells with fully half-select-free robust operation for bitinterleaving implementation. The proposed 11T-1 and 11T-2 cells successfully eliminate Read disturb and Write half-select disturb and also improve the Write-ability by using power-cutoff and write '0'/ '1' only techniques. The 11T-1 and 11T-2 cells achieve 1.83x and 1.7x higher write-yield while both achieve approximately 2x higher read-yield as compared with 6T cell (at V DD =0.9V). The proposed 11T-1 cell also shows 13.6% higher mean Write-margin (WM) compared with existing 11T cell. Both the proposed cells successfully eliminate floating node condition encountered in earlier power cutoff cells during write half-select. Monte-Carlo simulation confirms low-voltage operation without any additional peripheral assist circuits. We also present a comparative analysis of Bias Temperature Instability (BTI) reliability impacting the SRAM performance in a predictive 32nm high-k metal gate CMOS technology. Under static stress, the Read Static Noise Margin (RSNM) reduces for all cells. However, 11T-1 and 11T-2 cells improve RSNM by 2.7% and 3.3% under relaxed stress of 10/90. Moreover, the proposed 11T-1 (11T-2) cell improves WM by 7.2% (13.2%), reduces write power by 28.0% (20.4%) and leakage power by 85.7% (86.9%), degrades write delay by 38.1% (23.3%) without affecting read delay/power over a period of 10 8 seconds (approx. 3 years). The 11T-1 (11T-2) cell exhibits 4.8% higher (2% lower) area overhead as compared to earlier 11T cell. Hence, the proposed 11T cells are an excellent choice for reliable SRAM design at nanoscale amidst process variations and transistor aging effect and can also be used in bit-interleaving architecture to achieve multi-cell upset (MCU) immunity.
TRAM: a tool for temperature and reliability aware memory design
2009
Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage V dd and temperature on memory performance and their interrelationships. We propose a Temperature-and Reliability-Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware V dd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors.