BooleDozer: Logic synthesis for ASICs (original) (raw)

SKOL: a system for logic synthesis and technology mapping

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991

This paper describes SKOL, a system for the synthesis of combinational logic using a library of cells, with emphasis on the technology mapping algorithms. It combines current multilevel optimization techniques with a new approach to the technology mapping problem. This approach is characterized by the use of a numerical string for representing the Boolean expressions and the library cells, which allows a fast selection process. Technology mapping is performed directly on the factored Boolean network, without decomposing it into primitive gates. A dynamic programming approach is used for mapping the whole Boolean network based on the possible matches for each node. Results from benchmark examples show that this approach is effective in reducing the final cell count. Comparisons with existing systems are presented.

Design of Framework for Logic Synthesis Engine

International Journal of Engineering and Technology, 2013

Logic synthesis is a novel architectural concept used for converting a high level description of logic circuit into optimized gate level description. The method ranges from transforming a RTL description to producing an optimized netlist. Logic minimization plays an important role in optimization of logic synthesis. This optimization is done through the function minimization through different existing methods. The existing work on function minimization has resulted into many algorithms. In the proposed work, we form the basis for our synthesis engines vide detailed performance analysis and insight into the various minimization algorithms proposed erstwhile, and apply them on some real example circuit. We plan to propose our own algorithm as well for enhanced performance.

Layout driven logic synthesis system

IEE Proceedings - Circuits, Devices and Systems, 1995

In a system level or logic level design process, the decisions made during early phases of the high level design have the greatest impacts on the performance of the final chip. However, these impacts will not be realised until very late in the physical design stage. In addition, it has been observed repeatedly that the most frustrating problem in IC design is to understand the relationship between the early phase decisions and the final layout result. It is therefore important, in logic synthesis to optimise a cost function which could relate the logic equation and the final layout performance. The authors develop a logic synthesis approach which relies on an accurate design evaluation program to estimate the final design attributes such as layout area and speed. Given a candidate design implementation, an evaluation programme will be called upon to provide quick and accurate estimates of the layout area or critical path delay. This information will then be used as a feedback to the logic optimisation system. Based on this feedback, the system will 'reorient' itself toward a new direction for optimisation. Such a scheme represents a more realistic way of generating optimal layout implementations. m c IEE, 1995 Paper 19256 (ElO), first received 15th September 1994 and in revised form 27th February 1995 Y . Chen is with the Hitachi

A Comprehensive Set of Logic Synthesis and Optimization Examples

2016

In this paper we introduce a new set of example circuits, primarily intended for using in logic synthesis and optimization, mostly for testing and benchmarking purposes. Basically, the proposed set of circuits is a collection of former popular benchmark sets. By putting these circuits together, we have formed a more comprehensive, but unified and well-arranged set of example circuits, from which a user can select circuits (or the whole benchmarks) upon his wishes and needs. The collection comprises of several sets, which, even though they sometimes contain the same circuits, are customized to particular needs of the user. This paper documents the example set, together with origins of its parts, and statistics on the circuits are provided.

Design-Flow and Synthesis for ASICs: A Case Study

32nd Design Automation Conference, 1995

The growing complexity of devices to be designed and manufactured, and the need to reduce the time-to-market, stress the importance of sound design methodologies. In this framework formal synthesis has the advantage of increasing the quality both of the design process and of the realized devices. The problem of relating the different abstraction levels involved in the extended design process is solved through the use of logic synthesis tools. The evaluation of the design constraints, characterizing optimal implementations such as area and timing, provide the most pragmatic approach to identify efficient guidelines applicable in the abstract phases of the design flow. The resulting design methodology combining both formal and more traditional design tools has been tested on a complex device in the area of telecommunications.

ATPG-based logic synthesis: an overview

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002., 2002

The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is expressed using "don't cares" and we seek the best implementation that does not violate them. However, the calculation and storing of don't care information is CPU and memory-intensive. In this paper, we give an overview of logic synthesis approaches based on techniques developed for Automatic Test Pattern Generation (ATPG). Instead of calculating and storing don't cares explicitly, ATPG-based logic synthesis techniques calculate the flexibility implicitly. Low CPU and memory usage make those techniques applicable for practical industrial circuits. Also, the basic ATPG-based logic level operations create predictable, small layout perturbations, making an ideal foundation for efficient physical synthesis. Theoretical results show that an efficient, yet simple add-a-wire-and-remove-a-wire operation covers all possible complex logic transformations.

Decomposition-based logic synthesis and its application in FPGA-oriented technology mapping

Decomposition-based logic synthesis and its application in FPGA-oriented technology mapping Summary: A generalized decomposition algorithm is formulated to map a Boolean function into a network of universal cells capable of implementing any function with a fixed number of inputs and outputs. The main characteristic of the method are original representation of Boolean functions as well as application of graph coloring heuristics to the serial decomposition problem. The method is applied to several standard benchmarks and the results presented. When the algorithm is targeted at a technology-specific cell structure, the cell count is reduced considerably.

Driven Logic Synthesis for Area and Power Minimization

2007

In this paper we present the application of our ATPGbased design rewiring approach to multi-level combinational logic circuit optimization. At every step of this optimization procedure, we introduce a design error by removing the logic that violates the optimization constraint(s) and then we attempt to correct the design by modifying the logic somewhere else. We give heuristics and describe the application of this method to delay optimization and to design for low power. Experiments are also presented to support the potential of our method. Ivor Ting Andreas Veneris Magdy S. Abadir Alcatel University of Toronto Motorola 4190 Still Creek Drive Dept ECE and CS 7700 W. Parmer Burnaby, BC V5C 6C6 Toronto, ON M5S 3G4 Austin, TX 78729 ivor.ting@alcatel.com veneris@eecg.toronto.edu m.abadir@motorola.com