How will photonic integrated circuits develop? (original) (raw)
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Integrated Photonics Research and Applications/Nanophotonics for Information Systems, 2005
The integration scale in Photonic Integrated Circuits will be pushed to VLSI-level in the coming decade. Key technologies for reduction of device dimensions are high resolution lithography and deep waveguide etching technology. In this paper developments in Photonic Integration are reviewed and the limits for reduction of device dimensions are discussed.
Intimate monolithic integration of chip-scale photonic circuits
IEEE Journal of Selected Topics in Quantum Electronics, 2000
In this paper, we introduce a robust monolithic integration technique for fabricating photonic integrated circuits comprising optoelectronic devices (e.g., surface-illuminated photodetectors, waveguide quantum-well modulators, etc.) that are made of completely separate epitaxial structures and possibly reside at different locations across the wafer as necessary. Our technique is based on the combination of multiple crystal growth steps, judicious placement of epitaxial etch-stop layers, a carefully designed etch sequence, and self-planarization and passivation steps to compactly integrate optoelectronic devices. This multigrowth integration technique is broadly applicable to most III-V materials and can be exploited to fabricate sophisticated, highly integrated, multifunctional photonic integrated circuits on a single substrate. As a successful demonstration of this technique, we describe integrated photonic switches that consume only a 300 × 300 µm footprint and incorporate InGaAs photodetector mesas and InGaAsP/InP quantum-well modulator waveguides separated by 50 µm on an InP substrate. These switches perform electrically-reconfigurable optically-controlled wavelength conversion at multi-Gb/s data rates over the entire center telecommunication wavelength band.
Integration of silicon photonics into electronic processes
Silicon Photonics VIII, 2013
Front-end monolithic integration has enabled photonic devices to be fabricated in bulk and thin-SOI CMOS as well as DRAM electronics processes. Utilizing the CMOS generic process model, integration was accomplished on multi-project wafers that were shared by standard electronic customers without requiring in-foundry process changes. Simple die or wafer-level post-processing has enabled low-loss waveguides by the removal of the substrate within photonic regions. The custom-process model of the DRAM industry instead enabled optimization of the photonic device fabrication process and the potential elimination of post-processing requirements. Integrated singlecrystalline silicon waveguide loss of ~3 dB/cm has been achieved within a 45nm thin-SOI CMOS process that is currently used to manufacture microprocessors [1]. A fully monolithic photonic transmitter including a pseudo-random bit sequence (PRBS) generating digital backend was also demonstrated within this process [1]. The constraints of zero-change integration have limited achieved polysilicon waveguide loss to ~50 dB/cm with commercially available bulk CMOS processes [2]. Custom polysilicon deposition and processing conditions available for DRAM integration have also led to the demonstration of ~6 dB/cm loss waveguides suitable for integration within electronics processes utilizing bulk silicon starting substrates [3]. An overview of required process features, device design guidelines and integration methodology tradeoffs will be presented. Relevant device metrics of area and energy efficiency as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe-art electronics processes. Applications of this research towards the implementation of a computer system utilizing photonic interconnect for core-to-memory communication will also be discussed.
Silicon Photonics X, 2015
We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-theart (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "Morethan-Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.
Miniaturization of Chip-Scale Photonic Circuits
2012
Chip-scale photonic circuits promise to alleviate some fundamental physical barriers encountered in many areas of the life sciences and information technologies. This work investigates routes to miniaturization of chip-scale optical devices. Two new techniques and devices based thereon are introduced for the first time. One technique makes use of integrated metallic mirrors to construct reflectors which are by an order of magnitude smaller than their counterparts. Another technique is based on folding of chip-scale devices to fit long structures into small area on a chip. Although both techniques are demonstrated on some specific examples, the developed toolkit is xvi applicable to a wide range of chip-scale devices including modulators, filters, channel add-drop multiplexers, detectors, and others. The major part of this Thesis focuses on miniaturization of waveguide reflectors and the devices based thereon. Fitting long waveguide Bragg gratings into a small area on a chip is demonstrated based on curved waveguide Bragg gratings; theory and analytical model of such structures is developed. In the second part of the Thesis, integrated metallic mirrors are proposed as reflectors with properties complementary to Bragg gratings-low polarization sensitivity, high reflectivity for different transverse modes, and good manufacturability. The feasibility of the proposed ideas is tested in both simulations and experiments. The demonstrated devices including biochemical sensors, micro-resonators, and inline filters are promising for applications in the life sciences and information technologies.
(Invited) Silicon Photonics Technologies for Monolithic Electronic-Photonic Integrated Circuit
ECS Transactions, 2010
Severe information latency and power consumption are key technology challenges facing the traditional copper interconnects which impose tremendous constraints to keep up with the performance roadmap driven by the Moore's Law. Converging electronic and photonic integrated circuits (EPIC) on a single chip platform to enable functional diversification emerges as one promising approach which could be realized by taking the advantage of low energy and huge data capacity of optical interconnects. By leveraging on the wealth of CMOS technology know-how and infrastructures, the fundamental photonics building blocks constructing the EPIC platform have been successfully developed in this work. We present an overview on the current status of this critical technology development and provide an outlook for the monolithic integration of Si micro- and nano-photonics. It is our belief that a seamless integration of EPIC is poised to become a promising technology to meet the bandwidth and energy...
Electro-photonics: an emerging field for photonic integrated circuits
2018
Electro-Photonics combines the best of both electronics and optics to tackle the challenges of next generation optical communication networks in terms of capacity, flexibility, and energy efficiency. The optimal sharing of the processing work load between the electrical and optical domain brings considerable benefits to communication system complexity, performance, and construction as well as operational cost. As a key technology, photonic integrated circuits (PICs) play a critical role for the implementation of signal processing in the optical domain, serving for signal generation, switching, and acquisition. PICs point to advancing of network devices such as transmitters, receivers, and switches with desirable features of large bandwidth, high stability, precise control, easy tuning, and potential for low-cost fabrication by enabling miniaturization of complex optical systems on a chip scale. In this paper, we review the PIC research progress of the Monash Electro-Photonics Labora...
Devices and architectures for photonic chip-scale integration
Applied Physics A, 2009
Silicon nanophotonics holds the promise of dramatically advancing the state of the art in computing by enabling parallel architectures that combine unprecedented performance and ease of use with affordable power consumption. This paper presents a design study for a manycore architecture called Corona which utilizes dense wavelength division multiplexing (DWDM) for on-and off-chip communication together with the devices which will be needed to implement such a communication infrastructure. PACS 42.82.-m · 42.82.Ds · 42.82.Bq
Advanced integration schemes for high-functionality/high-performance photonic integrated circuits
SPIE Proceedings, 2006
The evolution of optical communication systems has facilitated the required bandwidth to meet the increasing data rate demands. However, as the peripheral technologies have progressed to meet the requirements of advanced systems, an abundance of viable solutions and products have emerged. The finite market for these products will inevitably force a paradigm shift upon the communications industry. Monolithic integration is a key technology that will facilitate this shift as it will provide solutions at low cost with reduced power dissipation and footprint in the form of highlyfunctional optical components based on photonic integrated circuits (PICs). In this manuscript, we discuss the advantages, potential applications, and challenges of photonic integration. After a brief overview of various integration techniques, we present our novel approaches to increase the performance of the individual components comprising highly functional PICs.