ASIC implementation of a hardware-embedded physical unclonable function (original) (raw)
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Analysis of Entropy in a Hardware-Embedded Delay PUF
Cryptography
The magnitude of the information content associated with a particular implementation of a Physical Unclonable Function (PUF) is critically important for security and trust in emerging Internet of Things (IoT) applications. Authentication, in particular, requires the PUF to produce a very large number of challenge-response-pairs (CRPs) and, of even greater importance, requires the PUF to be resistant to adversarial attacks that attempt to model and clone the PUF (model-building attacks). Entropy is critically important to the model-building resistance of the PUF. A variety of metrics have been proposed for reporting Entropy, each measuring the randomness of information embedded within PUF-generated bitstrings. In this paper, we report the Entropy, MinEntropy, conditional MinEntropy, Interchip hamming distance and National Institute of Standards and Technology (NIST) statistical test results using bitstrings generated by a Hardware-Embedded Delay PUF called HELP. The bitstrings are generated from data collected in hardware experiments on 500 copies of HELP implemented on a set of Xilinx Zynq 7020 SoC Field Programmable Gate Arrays (FPGAs) subjected to industrial-level temperature and voltage conditions. Special test cases are constructed which purposely create worst case correlations for bitstring generation. Our results show that the processes proposed within HELP to generate bitstrings add significantly to their Entropy, and show that classical re-use of PUF components, e.g., path delays, does not result in large Entropy losses commonly reported for other PUF architectures.
Performance evaluation of Physically Unclonable Function by delay statistics
2011 IEEE 9th International New Circuits and systems conference, 2011
This paper presents a novel approach to evaluate silicon Physically Unclonable Functions (PUFs) implemented in FPGAs and based on delay elements. The metrics studied to characterize the PUFs are Randomness, Uniqueness and Steadiness. They take advantage of the measured physical values of elementary component making up the PUF. The delay distributions provide the interest to quantify the PUF at the physical level rather than carrying out a lot of experiments to get the PUF IDs at logical level. An Arbiter PUF composed of identical chains has been considered as a test chip to evaluate the method with the proposed metrics. Experiments have been carried out on CYCLONE II FPGA and the corresponding results shows the intra-device performance of the studied PUF.
DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices
2021
In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required proce...
Innovative Systems Design and Engineering, 2017
Physical Un-clonable Function (PUF) is a physical entity that provides secret key or fingerprints in silicon circuits by exploiting the uncontrollable randomness during its manufacturing randomness. It provides a hardware unique signature or identification. Its property of uniqueness comes from its unpredictable way of mapping challenges to responses, even if it was manufactured with the same process. Previous work has mainly focused on novel structures for non-FPGA reconfigurable silicon PUFs which does not need any special fabrication method and which can overcome the limitations of FPGA-based simulations. Their performance was quantified by the inter-chip variations, intra-chip variations and re-configurability tests to meet practical application needs. This paper presents a novel approach of designing a low power non-FPGA feed-forward PUF using double gate MOSFET and also to analyze its parameters such as intra-chip variation, reliability and power. Keywords: Physical Un-clon...
Leveraging Distributions in Physical Unclonable Functions
Cryptography
A special class of Physical Unclonable Functions (PUFs) referred to as strong PUFs can be used in novel hardware-based authentication protocols. Strong PUFs are required for authentication because the bit strings and helper data are transmitted openly by the token to the verifier, and therefore are revealed to the adversary. This enables the adversary to carry out attacks against the token by systematically applying challenges and obtaining responses in an attempt to machine learn, and later predict, the token's response to an arbitrary challenge. Therefore, strong PUFs must both provide an exponentially large challenge space and be resistant to machine-learning attacks in order to be considered secure. We investigate a transformation called temperature-voltage compensation (TVCOMP), which is used within the Hardware-Embedded Delay PUF (HELP) bit string generation algorithm. TVCOMP increases the diversity and unpredictability of the challenge-response space, and therefore increases resistance to model-building attacks. HELP leverages within-die variations in path delays as a source of random information. TVCOMP is a linear transformation designed specifically for dealing with changes in delay introduced by adverse temperature-voltage (environmental) variations. In this paper, we show that TVCOMP also increases entropy and expands the challenge-response space dramatically.
Microprocessor Based Physical Unclonable Function
2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017
Research on Physical Unclonable Functions (PUF) is well established topic in the field of hardware security. PUF is useful in many security applications like IC metering, IP protection and cryptographic key generation. The PUF circuits proposed in the past are dedicated circuits which are extra overhead in terms of area and power. Utilizing the existing circuit structures like microprocessor, power rails, etc to design PUF can be seen in recent literature. In this paper, we propose a PUF topology based on microprocessor and CRP generation method. We present the interim result in terms of hamming distance to prove sufficient randomness in path delays in the hardware multiplier of OpenMSP430 microprocessor which can be exploited to design the PUF. The simulation and statistical analysis technique is also discussed.
Secure lightweight obfuscated delay-based physical unclonable function design on FPGA
Bulletin of Electrical Engineering and Informatics, 2022
The internet of things (IoT) describes the network of physical objects equipped with sensors and other technologies to exchange data with other devices over the Internet. Due to its inherent flexibility, field-programmable gate array (FPGA) has become a viable platform for IoT development. However, various security threats such as FPGA bitstream cloning and intellectual property (IP) piracy have become a major concern for this device. Physical unclonable function (PUF) is a promising hardware fingerprinting technology to solve the above problems. Several PUFs have been proposed, including the implementation of reconfigurable-XOR PUF (R-XOR PUF) and multi-PUF (MPUF) on the FPGA. However, these proposed PUFs have drawbacks, such as high delay imbalances caused by routing constraints. Therefore, in this study, we explore relative placement method to implement the symmetric routing in the obfuscated delay-based PUF on the FPGA board. The delay analysis result proves that our method to implement the symmetric routing was successful. Therefore, our work has achieved good PUF quality with uniqueness of 48.75%, reliability of 99.99%, and uniformity of 52.5%. Moreover, by using the obfuscation method, which is an Arbiter-PUF combined with a random challenge permutation technique, we reduced the vulnerability of Arbiter-PUF against machine learning attacks to 44.50%.
Design and evaluation of a delay-based FPGA physically unclonable function
2012
A new Physically Unclonable Function (PUF) variant was developed on an FPGA, and its quality evaluated. It is conceptually similar to PUFs developed using standard SRAM cells, except it utilizes general FPGA reconfigurable fabric, which offers several advantages. Comparison between our approach and other PUF designs indicates that our design is competitive in terms of repeatability within a given instance, and uniqueness between instances. The design can also be tuned to achieve desired response characteristics which broadens the potential range of applications.
Physical unclonable function and true random number generator: a compact and scalable implementation
2009
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile secret keys, whereas TRNGs are used for generating random padding bits, initialization vectors and nonces in cryptographic protocols. This paper proposes a scalable design technique to implement both a delay-based PUF and a jitter-based TRNG using ring oscillators. By sharing and reusing a significant amount of hardware resources, we achieve nearly 50% area reduction as compared to discrete implementations. We also propose and demonstrate a co-processor-based design that renders the circuit portable across various embedded processor platforms on FPGAs. Multiple scaled designs using 32 to 128 ring oscillators have been implemented and verified on Xilinx Spartan3S500E FPGA. A representative design uses 32 3-inverter ring oscillators, 64 flipflops/latches, 31 2-input XOR gates and control circuitry giving a 3.2Mbps truly random stream and 31-bit unique device signature.
Reliability and security of arbiter-based physical unclonable function circuits
International Journal of Communication Systems, 2012
Physical unclonable functions (PUFs) are considered as a promising technology that would be used for secure key generation and storage, integrated circuit (IC) authentication, and chip-unique signature generation. On the basis of the delay variation of logic gates across ICs, PUF circuits could be used to generate secret keys attached to some challenge-response schemes. In this study, an arbiter-based PUF circuit is implemented on Xilinx Virtex 2 Pro field-programmable gate array (Xilinx, Inc., San Jose, CA, USA), and its identification capability, reliability, and security are investigated. For this purpose, we define and measure the parameters such as interchip variation and environmental noise, which are important in the identification process of different ICs. In order to test the resistance of PUF circuit against software attacks, we applied two approaches. In the first one, we use a support vector machine classifier, and attacks are considered as a classification problem. In the second one, linear programming technique is applied to find the delay variables corresponding to the linear model of the PUF circuit.