Foreword Special Section on Packaging for Micro/Nano-Scale Systems (original) (raw)

Challenges in the packaging of MEMS

Proceedings International Symposium on Advanced Packaging Materials. Processes, Properties and Interfaces (IEEE Cat. No.99TH8405)

The packaging of Micro-Electro-Mechanical Systems (MEMS) is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications. Currently much work has been done in the design and fabrication of MEMS devices but insufficient research and few publications have been completed on the packaging of these devices. This is despite the fact that packaging is a very large percentage of the total cost of MEMS devices. The main difference between IC packaging and MEMS packaging is that MEMS packaging is almost always application specific and greatly affected by its envirotient and packaging techniques such as die handling, die attach processes, and lid sealing. Many of these aspects are directly related to the materials used in the packaging processes. MEMS devices that are functional in wafer form can be rendered inoperable after packaging. MEMS dies must be handled only from the chip sides so features on the top surface are not damaged. This eliminates most current die pick-and-place fixtures. Die attach materials are key to MEMS packaging. Using hard die attach solders can create high stresses in the MEMS devices, which can affect their operation greatly. Lowstress epoxies can be high-outgassing, which can also affect device performance. Also, a low modulus die attach can allow the die to move during ultrasonic wirebonding resulting to low wirebond strength. Another source of residual stress is the lid sealing process. Most MEMS based sensors and devices require a hermetically sealed package. This can be done by pm~el seam welding the package lid, but at the cost of further induced stress on the die. Another issue of MEMS packaging is the media compatibility of the packaged device. MEMS unlike ICS often interface with their environment, which could be high pressure or corrosive. The main conclusion we can DISCLAIMER Portions of this document may be illegible in electronic image products. Images are produced from the best available original document. , , draw about MEMS packaging is that the package affects the performance and reliability of the MEMS devices. There is a gross lack of understanding between the package materials, induced stress, and the device performance. The material properties of these packaging materials are not well defined or understood. Modeling of these materials and processes is far from maturity. Current post-package yields are too low for commercial feasibility, and consumer operating environment reliability and compatibility are often difficult to simulate. With fu~her understanding of the materials properties and behavior of the packaging materials, MEMS applications can be fully realized and integrated into countless commercial and military applications.

Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011

This paper presents a 0-level packaging technology for (RF-)MEMS implementing vertical feedthroughs or through-Si-via's (TSVs) and metal bonding. A thinned capping substrate (100µm thick) equipped with Cu-coated TSVs is bonded to a MEMS substrate. The vertical feedthroughs lead to a smaller footprint and make the package ready for 3D integration. The CuSn/Cu metal bonding provides a hermetic seal for the package. A full fabrication process for thinned Caps with "chamfered" shaped TSVs (70-120µm diameter) has been developed. Highly yielding TSVs (close to 100%) displaying a resistance of a single via of less than 10m have been obtained. The performance of traversing transmission lines (CPWs) patterned on the MEMS wafer (implemented in 1µm thick Cu and connected with the external terminals via the microbumps and the TSVs) has been measured. FEM based thermo-mechanical modelling is applied in order to evaluate the critical stress points and to estimate the Cap-to-MEMS die deflection under an external pressures.

Parasitic effects reduction for wafer-level packaging of RF-MEMS

Arxiv preprint arXiv: …, 2007

In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The package concept used is based on a wafer-level bonding of a capping silicon substrate with throughsubstrate interconnect to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finiteelement electromagnetic simulations (Ansoft HFSS). Moreover, a preliminary analysis on the electromagnetic effects of the capping wafer bonding techniques (solder bump reflow and isotropic or anisotropic conductive adhesive [1]) is presented.

RF–MEMS wafer-level packaging using through-wafer interconnect

Sensors and Actuators A: Physical, 2008

In this paper, development of a wafer-level packaging (WLP) process suitable for RF-MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is wafer-level bonded to an RF-MEMS device wafer providing MEMS device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-wafer electrical vias and optional through-substrate cavities allowing for hybrid integration. The RF-MEMS device wafer and the capping substrate are bonded using either solder reflow or an electrically conductive adhesive. After solder bump formation and singulation, this packaging solution results in surface-mount technology compatible components. Moreover, the presented WLP solution allows hybrid integration of additional IC dies that are flip-chip bonded within the capping substrate cavities. joined as a PhD student the Centre for High Frequency Engineering, Cardiff University, UK, working in collaboration with Nokia. His research work covered large-signal time-domain measurement techniques at radio and microwave frequencies and nonlinear characterization and modelling of high-power high-frequency transistors such as silicon LDMOS FETs for telecommunication applications. From 2002 he is with the RF-IC design group at the was a post-doctoral fellow in the Electronic Instrumentation Laboratory, Delft University of Technology, dealing with research on technological aspects of integrated silicon sensor systems. Presently, he is with the Laboratory of High-Frequency Technology and Components (HiTeC), Delft University of Technology, as an assistant professor, working in the area of system integration and wafer-level packaging for RF applications.

Hermetically sealed on-chip packaging of MEMS devices

2000

While packaging technology of conventional integrated circuits has already become more and more complex, packaging of MEMS sensors is particularly challenging. MEMS require a higher level of dedication given the fragility of the devices and the frequent need of a controlled atmosphere (e.g. gas mixture, overpressure or vacuum) in order to achieve the proper functionality of the devices. The actions taken to meet the desired specifications typically result in large, complicated and costly packages. The hermiticity of the package over the full life-time of the MEMS device is one of the largest challenges because of a large number of vacuum feedthroughs. Using the so-called indent-reflow sealing process, we have been able to demonstrate a hermetically-sealed on-chip vacuum package. As a result, a standard global package can be used.

Influence of 0-level packaging on the microwave performance of RF-MEMS devices

31st European Microwave Conference, 2001, 2001

are made of moveable and fragile structures (membranes, beams, cantilevers,…) that must be encapsulated for protection and for stable performance characteristics. Zerolevel or wafer-level packaging developed so far has been limited to dc-components. This paper elaborates on the design and fabrication of a 0-level package for housing RF-MEMS devices. The fabrication process is described and packages are characterized in terms of mechanical strength, hermeticity and microwave performance in the range 1-50 GHz. Simulations and experiments show minimal impact of the package on the RF losses if the cap has a minimal height of 50 µm, if low-loss materials (e.g., glass) are used, and if matched RF feedthroughs are implemented. Finally, in a multi-switch design, we recommend to minimize the number of feedthroughs, i.e. to use a single cap for the entire design.

3 RF‑MEMS packaging by using quartz caps and epoxy polymers

failure, these devices must therefore be protected by an appropriate package, able to ensure a stable and clean environment but also the redistribution of the electrical signals to the external world. Because of these specific constraints, the package has thus to be carefully designed taking into account the specific device characteristics. In addition, the realization of a such a package can be complex and very often presents severe fabrication compatibility issues. The final result of the overall package implementation difficulties is that frequently the cost of the package is comparable or higher than the cost of the rF MeMS device itself, limiting the exploitation of the rF-MeMS technologies for many promising applications.

A Stamp-Sealed Microshell Package for RF MEMS Switches

ASME 2007 InterPACK Conference, Volume 1, 2007

This paper describes a unique method of encapsulating MEMS switches at the wafer level using a thin-film "microshell" lid and a novel micro-embossing, or "stamping" technique to seal the lid. After fabrication of the MEMS switch and subsequent formation of the microshell, the switches are released through gold tunnels that allow the penetration of a chemical etchant. In a controlled ambient, a "stamp" wafer is aligned to the device wafer, and the wafers are thermally compressed together. This process applies pressure across each tunnel to fuse the gold, thereby sealing the microshell packages. By sealing and passivating the switches at the wafer level, the wafers can be exposed to backend processing, packaging, and assembly steps such as dicing without damaging the sensitive MEMS devices. Furthermore, the size, cost, and complexity of the packaged system are significantly reduced compared to standard wafer bonding processes.

Single wafer encapsulation of MEMS devices

IEEE Transactions on Advanced Packaging, 2003

Packaging of micro-electro-mechanical systems (MEMS) devices has proven to be costly and complex, and it has been a significant barrier to the commercialization of MEMS. We present a packaging solution applicable to several common MEMS devices, such as inertial sensors and micromechanical resonators. It involves deposition of a 20 μm layer of epi-polysilicon over unreleased devices to act as a