InP DHBT technology for 100 Gbit/s applications (original) (raw)
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InP DHBT-based IC technology for high-speed data communications
2005
In this paper, we report the achieved performance of devices and integrated circuits (ICs) using a manufacturable InP DHBT-based technology. High speed MBE grown InGaAs/InP DHBTs with an effective emitter junction area of 4.8 /spl mu/m/sup 2/ exhibited peak f/sub T/ and f/sub MAX/ values of 265 and 305 GHz, respectively, at a collector current density of 3.75 mA//spl mu/m/sup
Solid source MBE growth on InP-based DHBTs for high-speed data communication
Journal of Crystal Growth, 2007
We report on the development of a double heterojunction bipolar transistor (DHBT) technology on InP substrates for high-speed data communication. The technology is based on DHBTs with an InP emitter, a graded InGaAs:C base and a composite InGaAs/InGaAsP/ InP collector, grown by solid source phosphorous MBE. High carbon doping levels in the base layer with excellent carrier mobility values allow the fabrication of devices with DC current gain $90 and cutoff frequencies beyond f t ¼ 265 GHz. Using this technology, integrated circuits, including lumped amplifiers, voltage controlled oscillators, multiplexers and demultiplexers, suitable for operation at 40 and 80 Gbit/s have been successfully fabricated.
Multi-wafer MBE grown InP-based DHBTs for millimeterwave and digital applications
physica status solidi (c), 2006
In this paper, we report the development and performance of a complete InP-based DHBT manufacturable technology from material growth to device and integrated circuits realizations. The InGaAs/InP DHBTs were grown in a multi-wafer solid phosphorus MBE system. High frequency devices with an effective emitter area of 4.8 µm 2 exhibited peak f T and f MAX values of 250 and 270 GHz, respectively, at a collector current density of ~4 mA/µm 2. Using this technology, distributed amplifiers and low power consumption selectors, have been successfully fabricated and tested above 80 Gbit/s.
InP DHBT-Based IC Technology for 100-Gb/s Ethernet
IEEE Transactions on Electron Devices, 2000
It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet). Due to its high speed and high breakdown voltage, the InP double-heterojunction bipolar transistor (DHBT) technology is particularly suited for signal processing and high-speed communication systems. This paper summarizes our InP DHBT device and integrated circuit (IC) technology developed for ≥ 100-Gb/s-class mediumscale mixed-signal ICs. Key features and issues important for the growth and manufacturing of InP DHBTs with step-graded collectors are first discussed. The molecular-beam-epitaxy-grown transistors have cutoff frequencies (f T and f max) of over 350 GHz, current gains of ∼90, and common-emitter breakdown voltages of > 4.5 V. Using this technology, we then fabricated and succeeded in 112-Gb/s testing of multiplexers and integrated clock and data recovery/1:2 demultiplexer ICs and modules with very clear eye waveforms. Using the same technology, a distributed amplifier intended for use as a modulator driver exhibited an output voltage swing of ∼2 V pp. These building-block ICs combine high-speed operation with high signal quality and enable 112-Gb/s opticalfiber transmission.
Ultra high-speed InP/InGaAs DHBTs with f t of 203 GHz
Journal of Semiconductors, 2009
InP/InGaAs/InP double heterojunction bipolar transistors (DHBTs) were designed for wide band digital and analog circuits, and fabricated using a conventional mesa structure with benzocyclobutene (BCB) passivation and planarization process techniques. Our devices exhibit a maximum f t of 203 GHz, which is the highest f t for DHBTs in mainland China. The emitter size is 1.0 × 20 µm 2. The DC current gain β is 166, and BV CEO = 4.34 V. The devices reported here employ a 40 nm highly doped InGaAs base region and a 203 nm InGaAsP composite structure. They are suitable for high speed and intermediate power applications.
InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s
IEEE Journal of Solid-state Circuits, 2006
In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both and max . The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600 mV pp . The extracted 40 GHz clock signal shows a phase noise as low as 98 dBc Hz at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of 4.8 V, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.
High current density and high power density operation of ultra high speed InP DHBTs
We report thermal design and characterization of high-current-density InP double heterojunction bipolar transistors (DHBT) designed for 150 GHz logic operation. Low thermal resistance DHBTs were obtained through the use of InP collectors and composite InGaAs/InP subcollectors containing as little as 12.5 nm InGaAs for ohmic contacts. When biased at Je = 8 mA/μm2 and Vce = 1.45 V (11.6 mW/μm2 dissipation), producing 370 GHz fτ and 459 GHz fmax, the devices exhibit only 69°C emitter junction heating. The DHBTs operate without destruction at 10 mA/μm2 at Vce= 2 V, a 20 mW/μm2 dissipation. We also report on the improvements obtained through reducing the InGaAs subcollector ohmic contact layer thickness for improved device heat-sinking into the substrate.
Solid-State Electronics, 2007
Traditional compound semiconductor HBT technologies do not allow for the independent design of the intrinsic and extrinsic collector regions commonly found in Si BJT and SiGe HBT technologies. By using a selectively implanted buried sub-collector (SIBS) to optimize the intrinsic collector for reduced transit time and extrinsic collector for reduced capacitance, InP DHBTs technologies can finally have the same flexibility. An improved 200 GHz InP DHBT technology for broadband amplifiers with good forward Gummel characteristics and a DC current gain exceeding 100 is presented. SIBS also allows the fabrication of two types of HBTs, one with a peak f T /f MAX of 208 GHz/225 GHz at I C = 26.2 mA and one with a peak f T /f MAX of 148 GHz/237 GHz at I C = 16.6 mA, on a single wafer, giving the circuit designer additional flexibility. A state of the art traveling wave amplifier with a 61 GHz 3 dB-bandwidth, 29 dB differential gain, and only 2.5 W total power dissipation is presented. At a 45 Gb/s data rate, a 11 V differential output swing is demonstrated while maintaining <0.3 ps of added RMS jitter and 8/8 ps rise/fall times. Compared to a traditional mesa technology, the SIBS technology increased the differential output voltage swing by 1.0 V.
A GaAsSb/InP HBT circuit technology
… Arsenide and Other …, 2006
A InP/GaAsSb/InP double-heterojunction bipolar transistor (DHBT) structure has been defined, realized by MBE epitaxy, and optimized, thanks to simulation based on in-depth physical characterizations. A circuitoriented technology has been developed, which has been validated by the design and fabrication of a full-rate (40 GHz clock) 40 Gbit/s D-FF.