A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects (original) (raw)

An efficient algorithm for fast parasitic extraction and passive order reduction of 3D interconnect models

Luis Silveira

Design, Automation, and Test in Europe, 1998

View PDFchevron_right

Generating Compact, Guaranteed Passive Reduced-Order Models of 3-D RLC Interconnects

Luis Silveira

IEEE Transactions on Advanced Packaging, 2004

View PDFchevron_right

Automatic generation of accurate circuit models of 3-D interconnect

Luis Silveira

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1998

View PDFchevron_right

Interconnect analysis: from 3D structures to circuit models

Luis Silveira

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1999

View PDFchevron_right

Techniques for including dielectrics when extracting passive low-order models of high speed interconnect

Alberto Sangiovanni Vincentelli

2001

View PDFchevron_right

Vlsi Interconnection Modelling Using a Finite Element Approach

UMESH KUMAR

Active and Passive Electronic Components, 1995

View PDFchevron_right

A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects

Weikai Sun

1996

View PDFchevron_right

Coupled Circuit-Interconnect Modeling and Simulation

Luis Silveira

VLSI: Integrated Systems on Silicon, 1997

View PDFchevron_right

INDUCTWISE: Inductance-Wise Interconnect Simulator

Profect Chen

2003

View PDFchevron_right

PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm

musthaffa musthaffa

Proceedings of the 1997 IEEE/ …, 1997

View PDFchevron_right

Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures

A. Van Genderen, Nick van der Meijs

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993

View PDFchevron_right

REDUCED-ORDER MACROMODELING OF COMPLEX MULTIPORT INTERCONNECTS

Ivan Maio

View PDFchevron_right

SPRIM: structure-preserving reduced-order interconnect macromodeling

Roland Freund

Proceedings of the 2004 IEEE/ACM International …, 2004

View PDFchevron_right

A Software Tool for 3D Meshing of VLSI Interconnect Structures

Kees-jan Van Der Kolk, Nick van der Meijs

View PDFchevron_right

A fast and accurate computation of interconnect capacitance

Sylvie Putot

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999

View PDFchevron_right

Efficient computation of interconnect capacitances using the domain decomposition approach

Raj Mittra

IEEE Transactions on Advanced Packaging, 1999

View PDFchevron_right

A Comparison of the Model Order Reduction Techniques for Linear Systems Arising from VLSI Interconnection Simulation

Hasan Dag

Applied Numerical Analysis & Computational Mathematics, 2004

View PDFchevron_right

A divide-and-conquer algorithm for 3D capacitance extraction [IC modeling

Fangqing Yu

2004

View PDFchevron_right

INDUCTWISE: inductance-wise interconnect simulator and extractor

Profect Chen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003

View PDFchevron_right

Multiple block structure-preserving reduced order modeling of interconnect circuits

Sheldon X.-d. Tan

Integration, the VLSI Journal, 2009

View PDFchevron_right

Special issue on Compact Interconnect Models for Giga Scale Integration

M. Jamal Deen

IEEE Electron Device Letters, 2000

View PDFchevron_right

Compact modeling and fast simulation of on-chip interconnect lines

Ehrenfried Seebacher, Daniel Ioan, Gabriela Ciuprina

IEEE Transactions on Magnetics, 2006

View PDFchevron_right

EMC Modelling and Optimization for Reducing Capacitances of Interconnections with Arbitrary Shape in Multilayer VLSI Circuits

BOYUAN ZHU

View PDFchevron_right

Fast parameters extraction of general three-dimension interconnects using geometry independent measured equation of invariance

Weikai Sun

33rd Design Automation Conference Proceedings, 1996

View PDFchevron_right

Fast parameter extraction of general interconnects using geometry independent measured equation of invariance

Weikai Sun

IEEE Transactions on Microwave Theory and Techniques, 1997

View PDFchevron_right

Efficient techniques for modeling chip-level interconnect, substrate and package parasitics

Peter Feldmann

Proceedings of the conference on Design, automation and test in Europe - DATE '99, 1999

View PDFchevron_right

A PEEC-based Methodology and a Hybrid Code for the Analysis of 3D Irregular Interconnects

Enrico Vialardi

2004

View PDFchevron_right

Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods

Pinaki Mazumder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

View PDFchevron_right

SPIDER: capacitance modelling for VLSI interconnections

Patrick Dewilde

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

View PDFchevron_right

Comments on “ParAFEMCap: A Parallel Adaptive Finite-Element Method for 3-D VLSI Interconnect Capacitance Extraction&#x201D

Mustafa Kuzuoglu

IEEE Transactions on Microwave Theory and Techniques, 2000

View PDFchevron_right