Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET (original) (raw)
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Cornell University - arXiv, 2019
Silicon bipolar impact ionization MOSFET offers the potential for realization of leaky integrated fire (LIF) neuron due to the presence of parasitic BJT in the floating body. In this work, we have proposed an L shaped gate bipolar impact ionization MOS (L-BIMOS), with reduced breakdown voltage (VB = 1.68 V) and demonstrated the functioning of LIF neuron based on positive feedback mechanism of parasitic BJT. Using 2-D TCAD simulations, we manifest that the proposed L-BIMOS exhibits a low threshold voltage (0.2 V) for firing a spike, and the minimum energy required to fire a single spike for L-BIMOS is calculated to be 0.18 pJ, which makes proposed device 194× more energy efficient than PD-SOI MOSFET silicon neuron (MOSFET silicon neuron) and 5 × 10 3 times more energy efficient than analog/digital circuit based conventional neuron. Furthermore, the proposed L-BIMOS silicon neuron exhibits spiking frequency in the GHz range, when the drain is biased at VDG = 2.0 V.
Electrical Tunability of Partially Depleted Silicon on Insulator (PD-SOI) Neuron
Solid-State Electronics, 2019
The hardware realization of spiking neural network (SNN) requires a compact and energy efficient electronic analog to the biological neuron. A knob to tune the response of the as-fabricated neuron allows the network to perform various functioning without altering the hardware. Earlier, our group has experimentally demonstrated an LIF (leaky integrate & fire) neuron on a highly matured 32 nm SOI CMOS technology. In this work, we have experimentally demonstrated electrical tunability of the same through its intrinsic charge dynamics based on impact ionization (II) enabled floating body effect. First, a tunable input threshold (V th) is achieved by changing the drain bias. Second, above threshold, a firing frequency (f) to input (V) sensitivity (df/dV) tuning is successfully demonstrated by controlling the SOI-MOSFET's current threshold. We show that both the independent control of sensitivity and threshold is fundamentally enabled by the non-linearity of the impact ionization based carrier dynamics. The SOI neuron provides equivalent electrical tunability to Resistor-Capacitor (RC) based LIF neurons without degrading its original area and power advantages for clock-less, asynchronous SNNs. Further, we show that the neuronal behavior (threshold and sensitivity) is a key determinant of network performance, specifically the learning accuracy. Such flexibility based on post-fabrication electrical tuning will be an attractive enabler for the SNN hardware.
A Solid-State Neuron for Spiking Neural Network Implementation
Engineering Letters, 2008
This paper presents a compact analog neuron cell incorporating an array of charge-coupled synapses connected via a common output terminal. The novel silicon synapse is based on a two stage charge-coupled device where the weighting functionality can be integrated into the first stage. A presynaptic spike to the second gate allows the charge under the first gate to drift onto the floating diffusion output stage to produce a current, or voltage spike. Parallel defined synapses are each assigned to the left hand side of a current mirror gate where the right hand side feeds into a thresholding inverter. The decay of the membrane potential is mimicked by the charge leakage through a reverse-biased diode, whose model is verified by comparing the simulations and measured data. Spice simulation results show that the proposed neuron cell is capable of capturing the summing and thresholding dynamics of biological neurons.
Design of CMOS based Neuromorphic Sensor Circuit Using Floating Gate MOSFET
2020
We presents an Amperometric sensor circuit based on Floating gate technology which emulate spike time dependent plasticity (STDP) of human brain. The cell/neuron membrane is composed of Na and K ions with which cell can learn and adapt in new environment. The proposed circuit stores information in the form of charge at the floating gate (FG) and adaptability/plasticity is simulated in terms of time dependent spikes. The spikes are generated as a cell membrane capacitor's charging/discharging voltage which in turn, is controlled from sodium and potassium feedback circuits. The circuit have been implemented at 45nm CMOS technology. It generates a modulated voltage spike in response to input stimuli controlling charge at the FG. Inspired from bio-physical neuron model the proposed sensor circuit have been developed with sub-threshold conduction of MOSFETs and thus, circuit operates at nA level current sensitivity. It occupies very less chip area (245µm) and low power consumption (3.3nW) with 1.1V supply. The circuit is highly suitable in bimolecular fields for bimolecular detection.
An ultra-compact leaky-integrate-and-fire model for building spiking neural networks
Scientific Reports, 2019
We introduce an ultra-compact electronic circuit that realizes the leaky-integrate-and-fire model of artificial neurons. Our circuit has only three active devices, two transistors and a silicon controlled rectifier (SCR). We demonstrate the implementation of biologically realistic features, such as spike-frequency adaptation, a refractory period and voltage modulation of spiking rate. All characteristic times can be controlled by the resistive parameters of the circuit. We built the circuit with out-of-the-shelf components and demonstrate that our ultra-compact neuron is a modular block that can be associated to build multi-layer deep neural networks. We also argue that our circuit has low power requirements, as it is normally off except during spike generation. Finally, we discuss the ultimate ultra-compact limit, which may be achieved by further replacing the SCR circuit with Mott materials.
Improved neuron MOS-transistor structures for integrated neural network circuits
IEE Proceedings - Circuits, Devices and Systems, 2001
The neuron MOS transistor is a recently discovered device which is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of summation, thereby simulating the function of biological neurons. A comprehensive set of neuron test transistors has been designed, where a number of input gates are coupled capacitively to a floating gate, which controls the channel current. Integrated circuits for neural network applications have also been designed, based on the neuron MOS transistors. These circuits include neuron CMOS inverters and A/D and D/A converters. To increase the accuracy of the neuron MOSFET structures, calibration techniques are proposed and tested. All the test structures and circuits are implemented by using a standard 0.8 pm double-polysilicon CMOS technology. Attention was paid to saving of the layout area and reducing power consumption.
This paper proposes a silicon neuron circuit which uses a slow-variable controlled leakage term to extend the repertoire of spiking patterns achievable in an integrate and fire model. The simulations reveal the potential of the circuit to provide a wide variety of neuron firing patterns observed in neocortex, including adapting and non-adapting, regular spiking, fast spiking, bursting, chattering, etc. The firing patterns of basic cell classes are obtained with a simple adjustment of four biasing voltages. The circuit operates in the sub-threshold regime, with time constants similar to biological neurons, and hence is suitable for use in systems requiring such operating speeds. Envisaged applications of the proposed circuit are in large-scale analogue VLSI systems for spiking neural network simulations, brain-inspired circuits for robotics and hybrid silicon/biology systems.
Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI
2021
In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.
Sensors, 2021
To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power ...
A New Digital Low Power Spiking Neuron
International Journal of Future Computer and Communication
This article presents an innovative reconfigurable parametric model of a digital Spiking Neuron (SN). The model is based on the classical Leaky Integrate and Fire (LIF) model with some unique modifications, allowing neuron configuration using seven different leak modes and three activation functions with dynamic threshold setting. Efficient hardware implementation of the proposed spiking neuron significantly reduces the area and power cost. The SN model is implementable requiring only 700 ASIC 2-inputs gates and is denser than IBM SN which is composed of 1272 gates. The proposed spiking neuron model can be expanded to support a larger recurrent neural network and is efficiently applied to audio applications. Performance evaluation has been carried out through a simple voice activation system design using 1000 SNs, demonstrating ultra-low power consumption of only 20uW and consuming an area of 0.03 mm2 using 28nm technology. Simulations of the proposed digital spiking neuron also demonstrate its ability to accurately replicate the behaviors of a biological neuron model.