Correctness of dataflow and systolic algorithms using algebras of streams (original) (raw)
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arXiv: Numerical Analysis, 2016
We propose a semantics of operating on real numbers that is sound, Turing-complete, and practical. It modifies the intuitive but super-recursive Blum-Shub-Smale model (formalizing Computer ALGEBRA Systems), to coincide in power with the realistic but inconvenient Type-2 Turing machine underlying Computable Analysis: reconciling both as foundation to a Computer ANALYSIS System. Several examples illustrate the elegance of rigorous numerical coding in this framework, formalized as a simple imperative programming language ERC with denotational semantics for REALIZING a real function fff: arguments xxx are given as exact real numbers, while values y=f(x)y=f(x)y=f(x) suffice to be returned approximately up to absolute error 2p2^p2p with respect to an additionally given integer parameter pto−inftyp\to-\inftypto−infty. Real comparison (necessarily) becomes partial, possibly 'returning' the lazy Kleenean value UNDEF (subtly different from bot\botbot for classically undefined expressions like 1/0). This asserts clos...
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Lecture Notes in Computer Science, 1994
In this paper, we present methods for eliminating higher-order quanti ers in proof goals arising in the veri cation of digital circuits. For the description of the circuits, a subset of higher-order logic called hardware formulae is used which is su cient for describing hardware speci cations and implementations at register transfer level. Real circuits can be dealt with as well as abstract (generic) circuits. In case of real circuits, it is formally proved, that the presented transformations result in decidable formulae, such that full automation is achieved for them. Veri cation goals of abstract circuits can be transformed by the presented methods into goals of logics weaker than higher-order logic, e.g. (temporal) propositional logic. The presented transformations are also capable of dealing with hierarchy and have been implemented in HOL90. ? This work has been partly nanced by a german national grant, project Automated System Design, SFB No.358.
A formal model of non-determinate dataflow computation
1983
Almost ten years ago, Gilles Kahn used the fixed point theory of Dana Scott to define a formal and elegant model of computation for determinate dataflow graphs, networks of determinate processes communicating asynchronously through unbounded channels. Kahn viewed each process as a function mapping each tuple of streams, or sequences of values, received through its input channels to the tuple of streams produced at its output channels. Determinacy was defined as the requirement that the mapping be functional--that for each input stream tuple there be only one possible output stream tuple. Although most useful computation can be accomplished with only determinate processes, there are many important, inherently non-determinate application areas to which Kahn''s theory cannot be applied. In this thesis, a formal model of computation for non-determinate networks is presented in which each possible computation of a network is represented by a scenario. A scenario is a pair consist...
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019
This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic circuit verification in the context of symbolic computer algebra. The paper offers a new insight into the arithmetic circuit verification problem, by viewing the computation performed by the circuit as the flow of digital data. In the proposed bit-flow model the circuit is modeled as a network of logic components satisfying a bit-flow conservation law. We prove that the value of the flow of data in the circuit is invariant throughout the circuit and use this to prove soundness and completeness of the rewriting technique, independently from the computer algebra arguments. The efficiency of the method is illustrated with impressive results for large integer multipliers. The verification system and benchmarks are offered in an open source software environment.
Proceedings of the 9th ACM SIGPLAN International Workshop on Functional Art, Music, Modelling, and Design, 2021
We introduce the W-calculus, an extension of the call-byvalue λ-calculus with synchronous semantics, designed to be flexible enough to capture different implementation forms of Digital Signal Processing algorithms, while permitting a direct embedding into the Coq proof assistant for mechanized formal verification. In particular, we are interested in the different implementations of classical DSP algorithms such as audio filters and resonators, and their associated high-level properties such as Linear Time-invariance. We describe the syntax and denotational semantics of the W-calculus, providing a Coq implementation. As a first application of the mechanized semantics, we prove that every program expressed in a restricted syntactic subset of W is linear time-invariant, by means of a characterization of the property using logical relations. This first semantics, while convenient for mechanized reasoning, is still not useful in practice as it requires re-computation of previous steps. To improve on that, we develop an imperative version of the semantics that avoids recomputation of prior stream states. We empirically evaluate the performance of the imperative semantics using a staged interpreter written in OCaml, which, for an input program in W , produces a specialized OCaml program, which is then fed to the optimizing OCaml compiler. The approach provides a convenient path from the high-level semantical description to low-level efficient code. Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.
Stateless Circuit Model toward a Theorem-proving Hardware Description Language
Ph.D Thesis, 2017
Computer systems are now an essential part of the infrastructure of modern societies, and any false operation of them may become a big problem. To prevent such a problem from happening, designs of computer systems should be verified comprehensively, and there is a technology for this purpose: formal methods. Formal methods enable rigorous verification on the basis of mathematics, and one of their major classes is model-checking. In model-checking method, a system is described as a state-based model, and a model-checking tool automatically scans all possible states to inquire required specifications. However, when computational resources are not enough to scan all states, model-checking tool abandons scan, and thus the verification result is not offered. This is called the state explosion problem. Model-checking cannot escape from the state explosion problem cause of its theoretical principle. Theorem-proving method is an another class of formal method. Verification in theorem-proving method is finding a proof which intends ``a design satisfies a specification.'' Theorem-proving has generally no relation to the state explosion problem. In the field of hardware design, theorem-proving has been applied in a manner that a circuit model is built on an existing theorem-proving language. Since it contains two theories: theory of circuits and theory of theorem-proving, the model under consideration absolutely becomes complex. As a result, theorem-proving is not widely-used in this manner. Meanwhile, in the software design, there exists a language which enables programming and also theorem-proving, such as Coq and Agda. As each of them is based on a single theory, the language is relatively simple and has a potential to grow popular. By learning these programming languages, this thesis is toward these unified languages in the hardware field; it aims to realize hardware description language (HDL) with theorem-proving. Toward a theorem-proving HDL, a circuit model compatible with some logical system is required, and this thesis provides two circuit models: feedback-leap model and stateless model. Feedback-leap model resembles conventional feedback-loop model, but its expressive power becomes a little higher. A logical system for this model is provided, thus theorem-proving is available. The only drawback is that the model is based on state expression. Hopefully, it is better that a circuit model which is not based on state expression because one purpose of this thesis is to avoid the state explosion problem. The other model provided is stateless model, without state expression. A logical system is also attached, and theorem-proving verification of a asynchronous circuit is exhibited. Therefore, stateless model clears the minimum requirement for a basis of theorem-proving HDL. With respect to stateless model, a special kind of question emerges: how to characterize well-known state-based circuits -- synchronous circuits. This question could be a touchstone of the model's worth; generally speaking, circuit models are good if they can naturally characterize any class of intuition-friendly circuits, such as synchronous circuits. As a consequence, the characterization, called order-constructive, is determined, and thus stateless model's expressive power is guaranteed in a certain aspect. Furthermore, this characterization derives a conceptual new fact: a notion of circuit synchronization, or broad-sense synchronous. It represents common features of all kinds of synchronous circuits. To summarize, this thesis provides a prospective circuit model toward a theorem-proving HDL, and formal characterization of circuit-synchronization notion.
Logic and Algebra of Specification, 1993
An infinite synchronous concurrent algorithm (isca) is an algorithm composed of infinitely many modules and channels, computing and communicating in parallel, and synchronised by a global clock. A theory of such algorithms will explore infinite parallelism and also help in understanding computation involving unbounded finite parallelism. The theory presented is a generalisation of a theory of finite synchronous concurrent algorithms, based on computable functions on many sorted algebras. We use algebras to model specifications and iscas, and epimorphisms and isomorphisms to model related notions of implementation. We will model a hardware stack with unbounded capacity using an infinite synchronous concurrent algorithm and prove that the architecture is correct; special emphasis is placed on using algebras to formalise the various stages of the development. First we specify equationally a class of hardware stacks that operate in time with streams of data and commands. We then present a specific algebraic model StTop(S(X)) of the hardware stack axioms that computes over an arbitrary data set X and which serves as a mathematical specification for the hardware stack. Next we define an isca and we prove that this isca implements the model StTop(S(X)) of the stack. Finally we consider the refinement of the general algebraic model and isca over the set X to an algebraic model and isca based on the set {O, I} of bits.
On Algebras of Algorithms and Specifications over Uninterpreted Data
Formalized Mathematics, 2018
Summary This paper continues formalization in Mizar [2, 1] of basic notions of the composition-nominative approach to program semantics [13] which was started in [8, 11]. The composition-nominative approach studies mathematical models of computer programs and data on various levels of abstraction and generality and provides tools for reasoning about their properties. Besides formalization of semantics of programs, certain elements of the composition-nominative approach were applied to abstract systems in a mathematical systems theory [4, 6, 7, 5, 3]. In the paper we introduce a definition of the notion of a binominative function over a set D understood as a partial function which maps elements of D to D. The sets of binominative functions and nominative predicates [11] over given sets form the carrier of the generalized Glushkov algorithmic algebra [14]. This algebra can be used to formalize algorithms which operate on various data structures (such as multidimensional arrays, lists,...
A Proof-Producing Hardware Compiler for a Subset of Higher Order Logic
THEOREM PROVING IN …, 2005
Abstract. Higher order logic (HOL) is a modelling language suitable for specifying behaviour at many levels of abstraction. We describe a compiler from a 'synthesisable subset'of HOL function definitions to correctby-construction clocked synchronous hardware. The compiler ...