Thermal Investigations Of Flip Chip Microelectronic Package With Non-Uniform Power Distribution [TK7874. G614 2004 f rb] [Microfiche 7607] (original) (raw)

A study of the thermal characterization of a high — performance flip chip package

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2008

This paper describes a systematic experimental and numerical study of the thermal characterization of a flip-chip package. A cold-plate based test method is used for thermal characterization and internal thermal resistance is used as the basis of all comparisons. Experiment results are presented for three flip-chip packages.

Thermal performance of flip chip using finite element method

1998

This study deals with the use of finite element methods to determine the thermal performance and limits of flip chip packaging. The simulations show good agreement with available experimental data. The thermal limit study of the above package (based on the constraint of maximum junction temperature) shows that the limit of power dissipation is 1.7 W for the basic package under free convection and 1.9 W for forced convection. For the enhanced package (with heat sink), the limits are found to be 6.7 and 13.7 W for the cases of free and forced convection, respectively. This method offers greater ease of economical assessment of the thermal performance and limits of a variety of packages in comparison with other methods like CFD

Thermal performance of flip chip packages: Numerical study of thermo-mechanical interactions

Computational Materials Science, 2008

Excessive heat and temperature gradient may introduce failures in the components, such as cracking, delamination and warpage, eventually causing device failure. While there has been significant research toward understanding the thermal performance of many different electronic packages, the majority of these studies do not take into account the combined effects of thermal and mechanical interactions. This paper evaluates the thermal performance of flip chip packages based on the couple-field elements available in a numerical code, ANSYS, to study the interactions between temperature and stresses generated during the manufacturing process, where both two dimensional (2D) plane strain and three dimensional (3D) models of the flip chip package are considered. Compared with the model assuming uniform temperature distribution over the entire package, the model with temperature gradient provided more accurate stress profiles in the solder interconnections and underfill fillet. Further finite element studies based on the 2D model are conducted to evaluate the effects of thermal conductivity and substrate board configuration on the overall temperature and stress distribution in the package.

Thermal conduction analysis and characterization of solder bumps in flip chip package

Applied Thermal Engineering, 2012

Flip chip has been widely used in microelectronic packaging to meet the requirements of high density and optimal performance. With the shrinking of the package size, the heat dissipation problem is getting more serious, and the thermal modeling and measurement of flip chip have become hot topics. This paper investigated the thermal performance of the solder bumps using analytical and numerical methods. A lumped thermal resistance network was derived from the mathematical model of heat transfer in the flip chip structure. Common defects were introduced in the 3D finite element model. The impact of the defects on the heat conduction was investigated by the temperature distribution. The thermal performance of the solder bumps was characterized by using the thermal resistances. The relationship between the thermal resistance and the defects size was also studied, and the finite element model describes well the experimental data available from the literature. The results demonstrate that this model is effective for the thermal characterization of solder bumps, and can provide guidelines for failure detection in flip chip package.

Investigation of effects of heat sinks on thermal performance of microelectronic package

3rd IEEE International Conference on Adaptive Science and Technology (ICAST 2011), 2011

The concern about thermal performance of microelectronics is on the increase due to recent over-heating induced failures which have led to product recalls. Removal of excess heat from microelectronic systems with the use of heat sinks could improve thermal efficiency of the system. This paper investigates the effect of change in heat sink geometry on thermal performance of aluminium and copper heat sinks in microelectronics. Numerical studies on thermal conduction through an electronic package comprising a heat sink, chip, and thermal interface material were carried out. The thickness of the heat sink base and the height of the heat sink fins were varied in the study. The minimum and maximum temperatures of aluminium and copper heat sinks in the two models were investigated using steady state thermal conduction analysis. Better heat dissipation occurred in thinner base thickness and extended fins height for both aluminium and copper heat sinks. Aluminium heat sink recorded the lowest minimum temperatures in both investigations and is recommended as optimal thermal management material for heat sink production.

Thermal interface material performance in microelectronics packaging applications

Microelectronics Journal, 1997

The operation of near/y cvcvy electronic device generates heat, from the microprocessors used in computers, to mobile phone.Thc laws of physics dictate t/tat the performance and reliability of electronics and other integrated circuit dcvi,:es are absolutely constrained by device temperatures. Mathematicians have worked out formulae that indicate thatfor every 10°C vise in junction temperature the failure rate doubles. Petfovmance and reliability are jointly constrained by the manner in which electronic components are cooled and how the overall system attributes are handled. Heat is a major problem that ifleft unaddressed can cause problems at all stages of a product's l$e-cycle. Unless wejnd innovative ways to dissipate substantially move heat, there will be many move instances of equipmentfailure at a variety ofpoints in and around the enclosure and packaye-all of them temperature-related. This paper was originally pres,ented at IEPS (International Electronics Packaging Conference) during 1995.

Thermal analysis of a miniature electronic power device matched to a silicon wafer

Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010

This paper presents the power distribution modules of the WaferBoard TM system. These modules are critical components of these systems. In the proposed configuration, they are TCE (Thermal Coefficient of Expansion) matched to the WaferIC TM , a wafer scale device providing a configurable system connectivity. The paper provides results of steady state thermal management investigations that will contribute to its performance characterization. The paper deals with material selection, design, and validation of cooling mechanism to reduce localized hot spots and large thermal gradients. The performance of the proposed power distribution and thermal management strategy was evaluated and tested using a finite element method. Finally, this paper presents the methodology that was used to predict steady state thermal behavior of these critical power devices. It shows the resulting temperature profile when the wafer feeds power to a high performance chip enclosed in a standard package.