Associative memory design for the FastTrack processor (FTK) at ATLAS (original) (raw)

Next generation associative memory devices for the FTK tracking processor of the ATLAS experiment

Journal of Instrumentation, 2014

The AMchip is a VLSI device that implements the Associative Memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle trajectories at the ATLAS experiment at LHC. We present the architecture, design considerations, power consumption and performance measurements of the 4th generation of AMchip. We present also the design innovations toward the 5th generation and the first prototype results.

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

Journal of Instrumentation

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in high energy physics experiments. It contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 2 17 patterns. The AM06 integrates serializer/deserializer IP blocks at 2 Gbit/s for input/output communication, to avoid routing congestion at the board level. The AM06 is a complex chip. It has been designed in 65 nm CMOS, combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm 2 and contains 421 millions transistors. The AM06 can perform bitwise comparison at a rate of 100 kHz. Thanks to the XORAM cell and to the design optimization, the AM06 consumes about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

Journal of Instrumentation, 2014

The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input and output data are transmitted over serial links at 2 Gbit/s to reduce routing congestion at the board level. Prototypes of the AM chip and of the AM board have been manufactured and tested, in preparation of the imminent design of the final version.

A pipeline of associative memory boards for track finding

IEEE Transactions on Nuclear Science, 2001

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next Large Hadron Collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each

Performance Studies of the Associative Memory System of the ATLAS Fast Tracker

2018

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The system is one of the two main processing elements of FTK and is mainly based on the use of Application Specific Integrated Circuits, the AM chips, specifically designed to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. The AM system implementation is based on a collection of "AM boards", the "Serial Link Processors" (AMBSLP). The AMBSLP is based on a network of high speed serial links to sustain very high data traffic. It has a high power consumption (∼250 W) because of its high performance requirements and, therefore, the AM system needs custom power and cooling. This proceedings reports on the performance studies of the system made with the first production of 64 AMBSLPs integrated in FTK and results from the first ATLAS data during 2018.

Future evolution of the Fast TracKer (FTK) processing unit

2014

The Fast Tracker (FTK) processor for the ATLAS experiment has a computing core made of 128 Processing Units that reconstruct tracks in the silicon detector in a 100msec deep pipeline. The track parameter resolution provided by FTK enables the software-based High Level Trigger (HLT) trigger to efficiently identify and reconstruct significant samples of fermionic Higgs decays and other interesting physics processes. The data processing speed is achieved with custom VLSI pattern recognition, linearized track fitting executed inside modern FPGAs, pipelining, and parallel processing. One large FPGA executes full resolution track fitting inside low resolution candidate tracks found by a set of 16 custom ASIC devices, called Associative Memories (AM chips). For future fast tracking applications, the FTK dual structure which is based on the cooperation of VLSI dedicated AM and programmable FPGAs is maintained, but significant performance enhancements are achieved through miniaturization and...

The future evolution of the Fast Tracker processing unit

2015 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2015

Real time tracking is a key ingredient for online event selection at hadron colliders. The Silicon Vertex Tracker at the CDF experiment and the Fast Tracker at ATLAS are two successful examples of the importance of dedicated hardware to reconstruct full events at hadron colliders. We present the future evolution of this technology, for applications to the High Luminosity runs at the Large Hadron Collider where Data processing speed will be achieved with custom VLSI pattern recognition and linearized track fitting executed inside modern FPGAs, exploiting deep pipelining, extensive parallelism, and efficient use of available resources. In the current system, one large FPGA executes track fitting in full resolution inside low resolution candidate tracks found by a set of custom ASIC devices, called Associative Memories. The FTK dual structure, based on the cooperation of VLSI AM and programmable FPGAs, will remain, but we plan to increase the FPGA parallelism by associating one FPGA to each AM chip. Implementing the two devices in a single package would achieve further performance improvements, plus miniaturization and integration of the state of the art prototypes. We present the new architecture, the design of the FPGA logic performing all the complementary functions of the pattern matching inside the AM, the tests performed on hardware