Void Formation Study of Flip Chip in Package Using No-Flow Underfill (original) (raw)
Related papers
ECTC 2011, 2011
We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses pulsed amplitude pressure. A WLUF with 60% (weight) filler was applied by spin coating onto a wafer with Pb-free solder bumps. Following B-stage curing at 90 o C, the thickness was measured to be 20 microns over the solder bump height. In the B-staged state, this WLUF is stable at room temperature for several weeks. After the wafer was diced into chips, a chip was aligned and joined to a substrate with an optimized heating and cooling cycle. This WLUF assembly process has been evaluated using a flip chip test vehicle with 150 micron pitch and 3,300 area array solder bumps. The chip bumps were SnAg solder and the pre-solder on the substrate was SnAgCu. The size of the test chip was 9 x 13 mm and the test substrate was 42.5 x 42.5 mm. The test chip and substrate were designed to allow both two and four wire contact resistance measurements of the electrical interconnect structures. We successfully demonstrated 100% electrically and metallurgically good Pb-free joints. Voids inside the WLUF after flip chip bonding were decreased significantly using the pulsed amplitude pressure, post cure process. Scanning acoustic microscopy (SAM) analysis showed nearly void-free underfill bonding. After JEDEC level three preconditioning, environmental stress testing was completed and included 1000 deep thermal cycles of-55 to 125 o C; 1000 hrs at 85C/85% temperature and humidity; and 1000 hrs of 150 o C high temperature storage. Contact resistance measurements were made at time zero, after preconditioning and every 250 cycles or hours of environmental stress. The contact resistance measurements were stable on all parts. Detailed material and process development, and reliability test results are described in this paper.
No-flow underfill flip chip assembly––an experimental and modeling analysis
Microelectronics Reliability, 2002
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal-mechanical fatigue life of flip chips with no-flow underfill.
Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint
Journal of Electronic Packaging, 2004
The application of underfill materials to fill up the room between the chip and substrate is known to substantially improve the thermal fatigue life of flip chip solder joints. Nowadays, no-flow underfill materials are gaining much interest over traditional underfill as the application and curing of this type of underfill can be undertaken before and during the reflow process and thus aiding high volume throughput. However, there is always a potential chance of entrapping no-flow underfill in the solder joints. This work, attempts to find out the extent of underfill entrapment in the solder joints and its reliability effect on the flip chip packages. Some unavoidable underfill entrapments at the edges of the joint between solder bumps and substrate pads are found for certain solder joints whatever bonding conditions are applied. It is interesting to report for the first time that partial underfill entrapment at the edges of the solder joint seems to have no adverse effect on the fat...
Influence of underfill materials on the reliability of coreless flip chip package
Microelectronics and Reliability, 2008
A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn 3.0 Ag 0.5 Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260°C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young's modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011
This paper presents a systematic underfill selection and characterization methods for 21 × 21 mm 2 Cu/low-K flip chip packages (65 nm technology) with 150 µm bump pitch. This paper has also correlated the underfill characterization methods with the reliability results of 15 × 15 mm 2 and 21 × 21 mm 2 Cu/low-K flip chip packages. From the validations of underfill selection and characterization approach with the reliability of 21 × 21 mm 2 Cu/low-K flip chip package, it was found that the reliability results correlated well with the adhesion test results. Underfill/flux compatibility and underfill flow performance are found to be important factors during underfill selection. Underfill should not be sieved out at the initial stage without actual reliability tests.
IEEE Transactions on Electronics Packaging Manufacturing, 2002
Solder bumped Flip Chips on low cost substrates with three different epoxy-based no-clean flux liquid-like no-flow underfills are presented in this study. This paper includes evaluation of three commercial no-flow underfills and characterization of material and process parameters. Important materials and process parameters, such as curing temperature and time, thermal coefficient of expansion, storage modulus, loss modulus, tand, glass transition temperature, moisture uptake, solder reflow, and post curing are discussed in this work. Curing mechanism during reflow of no-flow underfills will be illustrated in this paper and a comparison of noflow underfill and conventional underfill will be also addressed. Also, cross-sections are examined for a better understanding of the effects of these no-flow underfill materials on the interconnects of the Flip Chip assemblies. Shear and thermal-cycling tests and results of these Flip Chip assemblies are reported and analyzed.
Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability
—In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic sub-strate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow under-fill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.
The Effect of Flux Residue and Substrate Wettability on Underfill Flow Process in Flip-Chip Packages
56th Electronic Components and Technology Conference 2006, 2006
The surface energies of different substrates and wetting angles of fluxes on the substrates were measured and showed differences between different substrates. The viscosity of fluxes at low stress shows a good correlation with their wetting properties. The modulus of flux residue varies significantly between different fluxes and high modulus flux residue is difficult to remove. The correlation between underfill, substrate properties, and underfill flow voids will be discussed. An underfill flow study with quartz die packages was conducted. The effect of flux residue and substrate wetting properties were assessed by this underfill flow study. This study will help us in minimizing the flux residue effect on underfill flow and optimizing underfill flow process.
IEEE Transactions on Components and Packaging Technologies, 2008
In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 C-240 C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill. Index Terms-finite-element analysis, flip chip, parametric study, phase change, Pb-free solder, strain energy release rate. I. INTRODUCTION S INCE the Pb-based solders have many advantages in cost, wetting characteristics, and availability in various melting temperatures, they have been widely used to provide electrical interconnection in electronics packaging. However, the use of Pb-based solders is being prohibited by the environmental regulations. Therefore, many studies have been performed
Development of wafer level underfill material and process
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003), 2003
The flip-chip on organic substrate has relied on underfill to enhance the solder joint reliability. The invention of the wafer level underfill technology has greatly improved the production efficiency of flip-chip process. The development of wafer level underfill material and process relies on the fundamental understanding of the underfill curing process. A wafer level underfill material is developed; its curing kinetics is modeled using autocatalytic model, based on which the B-stage feasibility of the underfill is investigated. The B-stage properties of the underfill are characterized in terms of its Tg, hardness, adhesion, dicing and storage capability. The developed wafer level underfill displays high curing latency required in the reflow process, as well as good mechanical properties after B-stage. The underfill is applied on a 6 inch bumped wafer and B-staged. Then the wafer is diced into individual components and assembled onto the FR-4 board.