IRJET- Realization of 8-Bit Pipelined RISC Processor using Verilog HDL (original) (raw)

Design of a 16-bit RISC Processor Using VHDL

International Journal of Engineering Research and, 2017

This paper targets the design and implementation of a 16-bit RISC Processor using VHDL (Very High Speed Integrated Circuit Hardware Description Language). As IC chip design involves complex computations and intense usage of resources, by using an HDL we can save resources and time by implementing it using the software approach. The implementation strategies have been borrowed from the popular MIPS architecture to a certain extent. The processor has 16-bit arithmetic and logical instruction set which has been designed and simulated. The instruction set is extremely simple and it gives an insight into the kind of hardware that would be required to execute the instructions accordingly. The ALU, instruction register, program counter, register file, control unit and memory have been integrated in the proposed processor. All the modules in the design are coded in VHDL to ease the description, verification, simulation and hardware implementation. The blocks are designed using the behavioral approach.

Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

Nepal Journal of Science and Technology, 2015

This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.

Risc Processor for Computer Hardware Introduction

International Journal of Modern Trends in Engineering and Research, 2015

Processors are the heart of all “smart” devices, whether they be electronic devices or otherwise. Their smartness comes as a direct result of the decisions and controls that processor makes.The existing commercial microprocessors are provided as black box units; with which users are unable to monitor internal signals and operation process, neither can they modify the original structure. In order to solve this problem 16-bit fully functional single cycle processor is designed in terms of its architecture and its functional capabilities. The procedure of design and verification for a 16-bit processor is introduced in this paper. The key architecture elements are being described, as well as the hardware block diagram and internal structure. The summary of instruction set is presented. This processor is modify as a VERILOG Hardware Description Language (VERILOGHDL) and gives access to every internal signal. In order to consume fewer resources, the design of arithmetic logical unit (ALU)...

Design and Implementation of 5 Stages Pipelined Architecture in 32 Bit RISC Processor

2012

The proposed work is the design of a 32 bit RISC (Reduced Instruction Set Computer) processor. The design will help to improve the speed of processor, and to give the higher performance of the processor. It has 5 stages of pipeline viz. instruction fetch, instruction decode, instruction execute, memory access and write back all in one clock cycle. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL. Particular attention will be paid to the reduction of clock cycles as well as to improve the speed of processor. This can be targeted to any FPGA for several applications. The processor will Synthesize using Xilinx Web pack and simulate using Model Sim simulator.

IJERT-Design of 16-bit RISC Processor

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/design-of-16-bit-risc-processor https://www.ijert.org/research/design-of-16-bit-risc-processor-IJERTV2IS70828.pdf The Reduced Instruction Set Computer or RISC is a microprocessor design principle that favours a smaller and simpler set of instructions that all take same amount of time to execute. RISC architecture is used across a wide range of platforms from cellular phones to super-computers. In this paper the behavioural design and functional characteristics of 16-bit RISC processor is proposed, which utilizes minimum functional units without compromising in performance. The design is based on Harvard architecture having separate data memory and instruction memory. The instruction word length is 24-bit wide. The processor supports 16 instructions with three addressing modes. It has 16 general purpose registers. Each register can store 16-bit data. The processor has 16bit ALU capable of performing 11 arithmetical and logical operations. The processor also incorporates a flag register which indicates carry, zero and parity status of the result. All the modules in the design are coded in Verilog. The individual modules are designed and tested at each level of implementation and finally integrated in a top level module by appropriate mapping. The design entry and synthesis is done using Xilinx ISE 10.1 tool and simulation results are verified using Modelsim 10.2.

Design of RISC-Based Processor on FPGA

The objective of this project was to design and implement a pipelined processor on FPGA using Xilinx (Spartan3E). We have used a RISC-like instruction set in the project. Instructions are 1-byte or 2-bytes depending on the type of instructions. There are four 1-byte general purpose registers; R0, R1, R2, and R3. For both RAM and ROM, the memory address space is 256 bytes and is byte addressable. PC is the program counter that points to the next instruction to be executed. For call subroutine instruction (BR.SUB) a special register, link register (LR), holds the address of instruction after BR.SUB.

Implementation of RISC Microprocessor for DSP Systems

This paper is about the reduced instruction set computer (RISC), microprocessor CPU design that flavors a smaller and simpler set of instruction. In this project we have described 16-bit pipelined RISC processor for applications such as in real time digital signal processor and embedded systems. The processor designed specifically for DSP systems such as FFT, DWT, Convolution and ALU, executes most of instructions in a single cycle; conventional processors usually performs only arithmetic and mathematical operations. Hence RISC processors have complex control system which requires more clock cycle to operate, thus we overcome this problem using pipelined architecture of 4 stages i.e fetch, decode, execute and write back. In fact compared to base paper the area is reduced and speed is increased. The Simulation is done on XILINX 14.5i tool, implemented on SPARTAN-6 kit. Over all speed is achieved and results are verified. Keywords: Reduced instruction set computer(RISC), Digital Signal Processor (DSP), Fast Fourier Transform(FFT), Discrete wavelet transform(DWT), VHDL ________________________________________________________________________________________________________

The HF-RISC Processor: Performance Assessment

This paper presents HF-RISC, a 32-bit RISC processor , along with its associated programming toolchain. The instruction set architecture of the processor is based on MIPS I and its hardware organization comprises three pipeline stages. The processor was synthesized in four different technology nodes for maximum frequency and simulated using CoreMark, an industry-standard performance evaluation benchmark. Using data obtained from synthesis and benchmarking we analyze the processor performance and compare it to similar commercial products. Obtained results indicate that HF-RISC is a good option for embedded design, as it presents performance figures similar to state-of-the-art ARM processors. Furthermore, its partially reconfigurable hardware organization allows the designer to explore performance and area trade offs.

Realization Of An 8-bit Pipelined Microprocessor in Verilog HDL

Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub process being divided segment that operates concurrently with all other segments. A pipeline may be visualized as a collection of processing segments through which binary information flows. Each segment performs partial processing segments dictated by the way the task is partitioned. The result obtained in one segment is transferred to subsequent segments in each step. The final result is obtained after the data has passed through all segments.This paper develops a code for the implementation of an 8-Bit microprocessor which implements instruction pipelining. After synthesis, an FPGA realization may be obtained . Simulation using Xilinx and ModelSim also produces favourable results which showcase the speedup (in terms of time) to carry out a program as compared to a non-pipelined version of this microprocessor.

VHDL Prototyping of a 5-STAGES Pipelined Risc Processor for Educational Purposes

This paper describes the VHDL (Very High Speed IC Hardware Description Language) implementation of a complete 5-stages, 32-bit, pipelined MIPS (Microprocessor without Interlocked Pipeline Stages) processor with integer multiplication and division support. The processor design supports all the 50 integer instructions including 25 R-type, 9 J-type and 16 I-type instructions. At the beginning, the processor's complete design is divided into three units: the pipelined datapath unit, the pipelined control unit and the hazard unit which solves all the problems of data hazards and control hazards. Then a program that finds the factorial of number 6 is executed and results are discussed. The VHDL design of the complete pipelined MIPS processor is implemented by using (Xilinx ISE Design Suite 13.4) program and configured on Xilinx Spartan-3AN FPGA (Field Programmable Gate Array) starter kit.