Reliability issues for flip-chip packages (original) (raw)
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Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance
2008 58th Electronic Components and Technology Conference, 2008
The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of fine-pitch, large-die Cu/low-k flip chip packages. In this paper, 3D finite element analyses were performed to investigate the reliability of 65nm, 21x21mm 9metal Cu/ low-k, chips with 150um interconnect pitch in a FCBGA package with a 750um die thickness and 1.0mm substrate thickness. Three parametric cases involving different geometries of solder joints were analyze: (A) All 20 rows with spherical solder joints, (B) 10 hourglass joints followed by 10 spherical joints, and (C) 10 spherical joints followed by 10 hourglass joints. The spherical joints are stiffer than the hourglass joints. It was found that Case C gave the lowest inelastic energy dissipation (∆W) for the critical solder joint implying that Case C will have the longest fatigue life. It was also found that Case C gave the lowest maximum stress in the low-k material and it was further shown that reliability will be enhanced with decrease in die thickness and substrate thickness.
Packaging effects on reliability of cu/low-k interconnects
IEEE Transactions on Device and Materials Reliability, 2003
Chip-packaging interaction is becoming a critical reliability issue for Cu/low-chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-dielectrics, packaging induced interfacial delamination in lowinterconnects has been widely observed, raising serious reliability concerns for Cu/lowchips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/lowinterconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on lowinterconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for lowinterfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moiré interferometry to investigate the chip-package interaction for lowinterconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/lowstructures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/lowstructures.
Influence of underfill materials on the reliability of coreless flip chip package
Microelectronics and Reliability, 2008
A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn 3.0 Ag 0.5 Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260°C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young's modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.
3rd IEEE International Conference on Adaptive Science and Technology (ICAST 2011), 2011
Solder joint is a method widely used to attach electronic chip on substrate. It is a generally knowledge that solder joint contains inter-metallic compound (IMC) at interconnects of solder bump and copper pads. The magnitude of IMC layer thickness impacts reliability of chip level packages. Extensive experimental investigations are conducted, however complementary numerical studies are needed to fully characterise the effects of IMC on high temperature reliability of flip chip (FC) assembly. In this work, thermo-mechanical response of FC lead-free solder joints to accelerated temperature cycle (ATC) is investigated using finite element analysis (FEA) code. The ANAND's model is employed to study the inelastic, nonlinear, rate dependent and visco-plastic behaviour of two models of FC48D6.3C457DC mounted on printed circuit boards (PCBs). While one model consists of conventional joints without IMC, the other is realistic with IMC embedded. In the result analysis based on damage indicators such as induced strain, stress, plastic work and hysteresis, it is found that negative impact of IMC on static structural integrity of solder joint operating at high temperature ambient is nontrivial.
Parametric finite element Analysis of solder joint reliability of flip chip on board
… Technology Conference, 1998. Proceedings of 2nd, 1998
Numerous studies have indicated that by encapsulating the solder joint with underfill material, the reliability of flip chip on board (FCOB) assemblies can be effectively enhanced. Typical manufacturing process for FCOB assembly with underfill, however, involves long throughput time and additional equipment sets which are undesirable for high volume manufacturing environments. Hence, desigdprocess simplification if not total elimination of underfill from the conventional FCOB assemblies that can directly result in productivity gain should be considered. A comprehensive parametric finite element analysis has been conducted to assess the feasibility of FCOB structures with partial underfill (i.e. only the peripheral joints are encapsulated with underfill material.) The effects of some critical design parameters such as die size, joint height, joint diameter, joint pitch, printed circuit board (PCB) thickness and material properties of underfill on the solder joint reliability of FCOB structure were investigated in this study. Two-dimensional nonlinear plane strain finite element models of FCOB package are employed. Moire and IR Fizeau interferometry technique are used to measure the thermal deformation of the FCOB for model validation. Elasto-plastic deformation behaviors of solder were simulated under thermal cyclic loading from-55 "C to 125 "C. Maximum effective elastic and plastic strains of the solder joint were calculated and used as the indicator for determining the solder joint reliability of the structures.
Microelectronics Reliability, 2006
To meet the future needs of high pin count and high performance, package size of flip-chip devices is constrained to become larger. In addition, to fulfill the environment issues, lead free solders will be replacing lead contained eutectic (Sn/37Pb) in near future. Thus, in this work, the effect of residual warpage and consequent residual stress on the reliability of large flip-chip using lead free solder is examined. Several effective experimental approaches to accurately measure residual warpage, using Moiré interferometry, shadow Moiré, and image processing schemes, are introduced. Moreover, geometric, process, and material parameters affecting the residual warpage during reflow process are discussed and some modifications are suggested. Finally, it is verified that it is crucial to accurately quantify and control the residual warpage in order to guarantee the overall reliability of flip-chip packages regardless of presence of underfill.
Impact of solder pad size on solder joint reliability in flip chip PBGA packages
1999
A variety of package parameters impact package reliability. One of the parameters that does not get much attention is the variations in package design that are assembly and vendor related. It was shown in this study that the solder pad size plays a big role in solder joint reliability. The difference in solder pad size due to different vendors and processes can affect the reliability considerably. In certain cases, the pad size effect can be so significant that it will override the effect of substrate thickness. Our work indicates that in order to obtain good correlations between predictive engineering results and reliability tests data, this factor should not be ignored. In this paper, finite element analysis was used to study the impact of substrate thickness on solder reliability for flip-chip PBGA (plastic ball grid array) packages. The simulation results were experimentally validated with moire interferometry. Both numerical and experimental results indicated that better solder reliability could be achieved by using thicker substrate. However, the size of BGA solder pad was found to be crucial to BGA life. In order to achieve higher C5 (controlled collapse chip carrier connection) reliability, a larger solder pad is preferred
Reliability of flip-chip interconnect for fine pitch applications
Flip chip assembly of die onto a substrate has been in existence since the 1960's. Today there is a great deal of interest in flip-chip technology, especially its use in chip scale packaging (CSP), where it has seen dramatic take-up in the mobile phone and display markets. Due to the continued drive to add further functionality to these products the trend in flip-chip interconnects is towards an ever finer pitch providing more I/O per square area of die. This trend is posing a number of challenges to package designers and board assemblers in terms of reliability. This paper discusses the results from a project investigating the manufacture and reliability of flip-chip interconnects at sub 100 micron pitch.
In this paper, a novel flip chip interconnect structure called Bond-On-Lead (BOL) and its ability to reduce stress in the sensitive sub-surface ELK (Extra Low K) layers of the die is presented. BOL is a new low cost flip chip packaging solution which was developed by STATSChipPAC to dramatically reduce the cost of flip chip packaging. The BOL solution allows for efficient substrate routing by virtue of the use of narrow BOL pads and the removal of solder mask in the area of the BOL pads, which eliminates the limitations associated with solder mask opening sizes and positional tolerances. In addition to the compelling cost benefits, modeling results are confirmed with empirical reliability testing data to show that BOL is superior to the traditional Bond-on-Capture Pad (BOC) configuration from a mechanical stress and reliability perspective. The focus of this paper is on the theoretical analysis of the stress, strain, and warpage associated with the BOL configuration compared with the traditional BOC structure. For the package deformation, the global finite element method is used to simulate the package warpage. For the local bumping reliability, the focus is on the ELK layers which are the critical locations affecting the package's reliability. The local finite element simulation is conducted to compare the critical ELK layers stresses with BOL structure vs. with traditional BOC structure.