Multi-core architecture with asynchronous clocks to prevent power analysis attacks (original) (raw)
Related papers
2008
Abstract Side channel attack based upon the analysis of power traces is an effective way of obtaining the encryption key from secure processors. Power traces can be used to detect bitflips which betray the secure key. Balancing the bitflips with opposite bitflips have been proposed, by the use of opposite logic. This is an expensive solution, where the balancing processor continues to balance even when encryption is not carried out in the processor.
2011
Abstract Side channel attackers observe external manifestations of internal computations in an embedded system to predict the encryption key employed. The ability to examine such external manifestations (power dissipation or electromagnetic emissions) is a major threat to secure embedded systems. This study proposes a secure multiprocessor architecture to prevent side channel attacks, based on a dual-core algorithmic balancing technique, where two identical cores are used.
An Efficient Hardware Countermeasure against Differential Power Analysis Attack
… and Hybrid Information …, 2011
Extensive research on modern cryptography ensures significant mathematical immunity to conventional cryptographic attacks. However, power consumption in cryptographic hardware leak secret information. Differential power analysis attack (DPA) is such a powerful tool to extract the secret key from cryptographic devices. To defend against these DPA attacks, hiding and masking methods are widely used. But these methods increase high area overhead and performance degradation in hardware implementation. In this aspect, this paper proposes a hardware countermeasure circuit, which, is integrated hardware module with the intermediate stages in S-Box. The countermeasure circuit utilizes the dynamic power dissipation characteristics of CMOS and provides countermeasure against DPA attacks.
Invariant of Enhanced AES Algorithm Implementations Against Power Analysis Attacks
Computers, Materials & Continua, 2022
The security of Internet of Things (IoT) is a challenging task for researchers due to plethora of IoT networks. Side Channel Attacks (SCA) are one of the major concerns. The prime objective of SCA is to acquire the information by observing the power consumption, electromagnetic (EM) field, timing analysis, and acoustics of the device. Later, the attackers perform statistical functions to recover the key. Advanced Encryption Standard (AES) algorithm has proved to be a good security solution for constrained IoT devices. This paper implements a simulation model which is used to modify the AES algorithm using logical masking properties. This invariant of the AES algorithm hides the array of bits during substitution byte transformation of AES. This model is used against SCA and particularly Power Analysis Attacks (PAAs). Simulation model is designed on MATLAB simulator. Results will give better solution by hiding power profiles of the IoT devices against PAAs. In future, the lightweight AES algorithm with false key mechanisms and power reduction techniques such as wave dynamic differential logic (WDDL) will be used to safeguard IoT devices against side channel attacks by using Arduino and field programmable gate array (FPGA).
A Low-Overhead Countermeasure against Differential Power Analysis for AES Block Cipher
Applied Sciences
This paper presents the employment of a DPA attack on the NIST (National Institute of Standards and Technology) standardized AES (advance encryption standard) protocol for key retrieval and prevention. Towards key retrieval, we applied the DPA attack on AES to obtain a 128-bit secret key by measuring the power traces of the computations involved in the algorithm. In resistance to the DPA attack, we proposed a countermeasure, or a new modified masking scheme, comprising (i) Boolean and (ii) multiplicative masking, for linear and non-linear operations of AES, respectively. Furthermore, we improved the complexity involved in Boolean masking by introducing Rebecca’s approximation. Moreover, we provide a novel solution to tackle the zero mask problem in multiplicative masking. To evaluate the power traces, we propose our custom correlation technique, which results in a decrease in the calculation time. The synthesis results for original implementation (without countermeasure) and inclusi...
Differential Power Analysis (DPA) Attack on Dual Field ECC Processor for Cryptographic Applications
Exchange of private information over a public medium must incorporate a method for data protection against unauthorized access. Elliptic curve cryptography is one of the best Public Key Cryptography algorithm as it provides high security at lesser bit sizes than RSA and also it operates with higher throughput, lower power consumption, and lesser area requirements .The Elliptic curve cryptography processor focuses on the analysis and counteracts of elliptic curve implementations against side-Channel attacks. When simple power analysis is not feasible differential power analysis can be tried. Differential Power Analysis tries to exploit the relationship between the processed data and the power consumption. To enhance the data security against the DPA attack in network communication, a dual field ECC processor supporting all finite field operations is proposed. A key-blinded technique is designed against power analysis attacks. The proposed ECC processor is designed using hardware description language and implement on FPGA to analysis individuality with other cryptographic algorithms.
Power analysis attack against encryption devices: a comprehensive analysis of AES, DES, and BC3
TELKOMNIKA Telecommunication Computing Electronics and Control, 2019
Cryptography is a science of creating a secret message and it is constantly developed. The development consists of attacking and defending the cryptography itself. Power analysis is one of many Side-Channel Analysis (SCA) attack techniques. Power analysis is an attacking technique that uses the information of a cryptographic hardware's power consumption. Power analysis is carried on by utilizing side-channel information to a vulnerability in a cryptographic algorithm. Power analysis also uses a mathematical model to recover the secret key of the cryptographic device. This research uses design research methodology as a research framework started from research clarification to descriptive study. In this research, power analysis attack is implemented to three symmetrical cryptographic algorithms: DES (Data Encryption Standard), AES (Advanced Encryption Standard), and BC3 (Block Cipher 3). The attack has successfully recovered 100% of AES secret key by using 500 traces and 75% DES secret key by using 320 traces. The research concludes that the power analysis attack using Pearson Correlation Coefficient (PCC) method produces more optimal result compared to a difference of means method.
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks
IEEE Transactions on Very Large Scale Integration Systems, 2018
Power analysis attacks (PAAs), a class of sidechannel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a registertransfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs. In the AES-128 exploiting SDRR, the combinational path evaluates random data throughout the entire clock cycle, and the interleaved processing of random and real data ensures the protection of both combinational and sequential logics. Our technique does not require the duplication of the combinational path to process the random data, thus limiting area overhead, unlike previous RTL countermeasures. The proposed approach is validated by means of PAAs based on real measurements on a field-programmable gate array implementation and on a 65-nm CMOS prototype chip. The protected implementation shows a strongly reduced correlation coefficient for the correct key, and more than three orders of magnitude increase in the measurements to disclosure with respect to the unprotected AES-128. Index Terms-Advanced encryption standard (AES), CMOS, correlation power analysis (CPA), differential power analysis (DPA), Internet of Things (IoT), mutual information (MI), power analysis attack (PAA), register-transfer level (RTL) countermeasure, side-channel attack (SCA).
A new dynamic differential logic style as a countermeasure to power analysis attacks
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 2008
Power analysis attacks exploit the existence of "side channels" in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods -such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) -for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential CMOS logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation.
FPGA - based evaluation of power analysis attacks and its countermeasures on Asynchronous S-Box
2014 International Conference on Electronics and Communication Systems (ICECS), 2014
A novel asynchronous S-Box design for AES cryptosystems is proposed and validated. The S-Box is considered as the most critical component in AES crypto-circuits since it consumes the most power and leaks the most information against side channel attacks. The proposed design completely based on a delay insensitive logic paradigm known as Null Conversion Logic (NCL). Asynchronous S-Box is based on self-time logic referred to as NCL which supports few beneficial properties for resisting SCAs such as clock free, duail rail encoding and monotonic transitions so that it consumes less power therefore suitable for energy constrained mobile crypto-applications. These beneficial properties make it difficult for an attacker to decipher secret key embedded within the cryptographic circuits of the FPGA board. Resistant to SCAs of both existing and proposed S-Box design are presented using differential power analysis (DPA) and correlation power analysis (CPA) attacks. The power measurement result showed that the NCL S-Box had lower total power consumption than original and effective against DPA and CPA attacks.