High Speed Redundant Adder and Divider in Output Prediction Logic (original) (raw)

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

Abstract

ABSTRACT A redundant bit adder (RBA) and a divider, both implemented in output prediction logic (OPL), are presented. By combining the carry-free nature of the redundant number system and the high-speed characteristics of OPL, the performance of the arithmetic blocks was tremendously improved. Fabricated in 0.18μm/1.8V CMOS, the adder achieves a measured delay of 211ps (2.4 fanout-of-four inverter delays), which is significantly faster than any previously published RBAs. The divider implemented in the same technology can achieve an operating frequency of 1.25GHz.

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