Thermal analysis of a multi-chip package design (original) (raw)

A thermal module design for advanced packaging

Journal of Electronic Materials, 1987

A hybrid silicon wafer-scale multi-chip packaging design was chosen as the basis for a high performance, high power dissipation vehicle suitable for VLSI/ULSI applications. The package supports 25 chips (l x l cm), each capable of dissipating as much as 40 W. The heat generated by the chips is removed by water channels in the underlying structure. Deep- (about 1000 μm), and shallow- (about 100 μm. deep), channel designs, with a water flow rate of 499 cc/sec, and 39 cc/sec, respectively, have been analyzed. Both designs are capable of keeping circuit temperature rise small, while maintaining a uniform chip temperature. The temperature distribution of the thermal module was obtained by solving the 2-D heat conduction equation for isolated heat sources (the chips), and heat sinks (the water channels). Assuming that each of the 25 chips dissipates 40 W/cm2, and heat is removed only via water flow, the maximum chip tempertaure(t cc which occurs at the center of a chip) rise relative to inlet water temperature is 11.4° C, and 19.0° C for the deep, and shallow designs, respectively. The maximumt cc variation between chips on the module (the same as the water temperature rise), for the cases analyzed, is 0.5° C for the deep-channel design, and 6° C for the shallow-channel design (calculated at 25° C inlet water temperature, and an optimum flow rate). For the extremely-uneven powered case (all chips except one at the inlet end are powered at 40 W/chip), the maximum temperature increases between inlet water temperature and chip temperature,t cc , remain relatively the same, but the maximumt cc variations between chips on the module increase to 11.4° C, and 19° C for the deep, and shallow designs, respectively, as might be expected. The temperature variation on a powered chip is less than 3° C for both the deep- and shallow-channel designs.

The need for a full-chip and package thermal model for thermally optimized IC designs

Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05, 2005

Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally selfconsistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip-and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.

Estimating the Thermal Interaction between Vertically Stacked Chips in a Multi-Chip package

Je-Young Chang received his B.S. and M.S. degrees from the Seoul National University in South Korea and his Ph.D. degree from University of Texas at Arlington, all in mechanical engineering. He worked at Penn State University for three years as a research associate before joining Intel in 2000. He has worked on many aspects of advanced cooling technologies, including twophase immersion cooling, single/two-phase microchannel cooling, corrosion reliability of liquid cooling systems, heat pipes, TIMs, heat exchangers, etc. He has 19 issued/pending US patents, and more than 60 articles in archival journals, conference proceedings and Intel internal publications.

Thermal management of packages with 3D die stacking

2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012

The objective of thermal design requirement for 3D stacked die package is to maintain the junction temperatures of active devices in the package at or below specified limits. In this paper, die-to-die thermal resistance is identified as the key bottleneck in 3D thermal management, and two solution paths are proposed: fully-populated thermal bump array and thermally conductive underfill materials. The sensitivity of the thermal bump array design and the effective thermal conductivity of underfill materials will be discussed. In addition to die-to-die thermal resistance reduction, enhancement of the overall packaging cooling capability by integrating liquid cooling to the package heat spreader is another option especially for the server type of environment which typically dissipates high power. An alternative approach is to integrate thermo-electric cooling to the heat spreader for hot spot cooling. For systems that are limited to traditional air cooling, this paper will propose a different package architecture which will utilize existing cooling capability of 3D die stacking. Although the power dissipation capability of 3D die stacking is worse than the 2D multiple-chip packages, dual-die stacking can potentially achieve a higher efficiency of "performance per power" by utilizing the same concept of dual-core microprocessor. This approach is very useful especially when the package real estate is limited and 3D die stacking is the preferred package architecture.

SOI Die Heat Transfer Analysis from Device to Assembly Package

The operational characteristics of silicon devices are strongly influenced by device temperature. For SOI devices power dissipation is a much more significant challenge than for non-SOI devices. As a result the thermal design of SOI devices is vital to proper product performance. To maximize the engineering understanding of SOI circuits we develop a method to examine the combined system of SOI device and the package by finite element analysis. These results are compared to results obtained from an equivalent electrical model. The use of on die structures as an aide to heat dissipation is explored.

Thermal Measurement and Modeling of Multi-Die Packages

IEEE Transactions on Components and Packaging Technologies, 2009

Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study we present results for a more complex structure: an opto-coupler device with 4 chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and MCM structures. It describes actual measurement results along with our structure function based methodology which helps validating the detailed model of the package being studied. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

Thermal modeling and management in ultrathin chip stack technology

IEEE Transactions on Components and Packaging Technologies, 2002

This paper presents a thermal modeling for power management of a new three-dimensional (3-D) thinned dies stacking process. Besides the high concentration of power dissipating sources, which is the direct consequence of the very interesting integration efficiency increase, this new ultra-compact packaging technology can suffer of the poor thermal conductivity (about 700 times smaller than silicon one) of the benzocyclobutene (BCB) used as both adhesive and planarization layers in each level of the stack. Thermal simulation was conducted using three-dimensional (3-D) FEM tool to analyze the specific behaviors in such stacked structure and to optimize the design rules. This study first describes the heat transfer limitation through the vertical path by examining particularly the case of the high dissipating sources under small area. First results of characterization in transient regime by means of dedicated test device mounted in single level structure are presented. For the design optimization, the thermal draining capabilities of a copper grid or full copper plate embedded in the intermediate layer of stacked structure are evaluated as a function of the technological parameters and the physical properties. It is shown an interest for the transverse heat extraction under the buffer devices dissipating most the power and generally localized in the peripheral zone, and for the temperature uniformization, by heat spreading mechanism, in the localized regions where the attachment of the thin die is altered. Finally, all conclusions of this analysis are used for the quantitative projections of the thermal performance of a first demonstrator based on a three-levels stacking structure for space application.

Integrated Thermal Management in System-on-Package Devices

Periodica Polytechnica Electrical Engineering and Computer Science

Thanks to the System-on-Package technology (SoP) the integration of different elements into a single package was enabled. However, from the thermal point of view the heat removal path in modern packaging technologies (FCBGA) goes through several layers of thermal interface material (TIM) that together with the package material create a relatively high thermal resistance which may lead to elevated chip temperature which causes functional error or other malfunctions. In our concept, we overcome this problem by creating integrated microfluidic channel based heat sink structures that can be used for cooling the high heat dissipation semiconductor devices (e.g.: processors, high power transistor or concentrated solar cells). These microchannel cooling assemblies can be integrated into the backside of the substrate of the semiconductor devices or into the system assemblies in SoP technology. In addition to the realization of the novel CMOS compatible microscale cooling device we have deve...