A Packet Generator on the NetFPGA Platform (original) (raw)
Related papers
NETFPGA: STATUS, USES, DEVELOPMENTS, CHALLENGES, AND EVALUATION
Journal of Engineering and Applied Sciences, 2020
The constant growth of the Internet, driven by the demand for timely access to data center networks has meant that the technological platforms necessary to achieve this purpose are outside the current budgets. In this order to make and validate relevant, timely and relevant contributions, it is necessary that a wider community, access to evaluation, experimentation and demonstration environments with specifications that can be compared with existing networking solutions. This article introduces the NetFPGA, which is a platform to develop network hardware for reconfigurable and rapid prototyping. It introduces the application areas in high-performance networks, advantages for traffic analysis, packet flow, hardware acceleration, power consumption and parallel processing in real time. Likewise, it presents the advantages of the platform for research, education, innovation, and future trends of this platform. Finally, we present a performance evaluation of the tool called OSNT (Open-Source Network Tester) and shows that OSNT has 95% accuracy of timestamp with resolution of 10ns for the generation of TCP traffic, and 90% efficiency capturing packets at 10Gbps of full line-rate.
Enabling open-source high speed network monitoring on NetFPGA
2012 IEEE Network Operations and Management Symposium, 2012
Network measurement both as diagnostic and within measurement-based techniques of traffic engineering and management, alongside network measurement for security has maintained the needs of researchers and network operators for the ongoing development of measurement tools for traffic monitoring/characterisation and to support Intrusion Detection Systems (IDSs). Many such tools capitalise on the pricing of commodity hardware by operating on general purpose architectures. Many are based on the well known libpcap API, a de facto standard in this area. Despite the many improvements that have been applied to packet capturing, packet-monitoring implementations still suffer from either: performance flaws on commodity hardware due mainly to unresolvable hardware bottlenecks, or costly and inflexible niche systems. To address such issues, the paper proposes a system architecture based on the cooperation of NetFPGA and a general purpose host PC. The NetFPGA is an open networking platform accelerator that enables rapid development of hardware-accelerated packet processing applications. The objective is to combine the high performance of a hardwareoriented solution with the flexibility of general purpose PCs.
A high-performance framework for a network programmable packet processor using P4 and FPGA
Journal of Network and Computer Applications, 2020
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
The P4->NetFPGA Workflow for Line-Rate Packet Processing
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
P4 has emerged as the de facto standard language for describing how network packets should be processed, and is becoming widely used by network owners, systems developers, researchers and in the classroom. The goal of the work presented here is to make it easier for engineers, researchers and students to learn how to program using P4, and to build prototypes running on real hardware. Our target is the NetFPGA SUME platform, a 4 × 10 Gb/s PCIe card designed for use in universities for teaching and research. Until now, NetFPGA users have needed to learn an HDL such as Verilog or VHDL, making it off limits to many software developers and students. Therefore, we developed the P4→NetFPGA workflow, allowing developers to describe how packets are to be processed in the high-level P4 language, then compile their P4 programs to run at line rate on the NetFPGA SUME board. The P4→NetFPGA workflow is built upon the Xilinx P4-SDNet compiler and the NetFPGA SUME open source code base. In this paper, we provide an overview of the P4 programming language and describe the P4→NetFPGA workflow. We also describe how the workflow is being used by the P4 community to build research prototypes, and to teach how network systems are built by providing students with hands-on experience working with real hardware.
Flexible, extensible, open-source and affordable FPGA-based traffic generator
Proceedings of the first edition workshop on High performance and programmable networking - HPPN '13, 2013
As high-speed links become ubiquitous in current networks, testing new algorithms at high-speed is essential for researchers. This task often requires traffic to be generated with some specified features : distribution of packet sizes, payload content, number of TCP or UDP flows... When targeting a data rate of many Gb/s, this cannot be done with commodity computers. Commercial traffic generators exist for this task, but they are expensive and do not fit the precise needs of researchers. In this paper, we describe an open-source implementation of a traffic generator capable of filling a 10 Gb/s Ethernet link, with traffic features specified in software. The implementation works on a board including an FPGA and a 10 Gb/s network interface, like the Combo from INVEA-TECH or the NetFPGA 10G. These boards are affordable for research and can provide a configurable and easily extensible traffic generator.
An open-source hardware module for high-speed network monitoring on netfpga
2010
We present a passive network measurement solution based on the low-cost NetFPGA-suitable for network research, security applications, and traffic engineering and management. Key features include accurate timestamping, and the ability to filter traffic based on flow. In this paper, we describe our implementation.
IJERT-FPGA based IP Core for High Performance Ethernet Frames
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/fpga-based-ip-core-for-high-performance-ethernet-frames https://www.ijert.org/research/fpga-based-ip-core-for-high-performance-ethernet-frames-IJERTV3IS061289.pdf Millions of people all over the world are using internet for sharing information. Therefore information access has become important asset, which demands reliable and effective tools for processing information. Networking is a technology used to share information between systems. As the number of connection between systems increases the IP address used increases, the number of servers, routers also increases. This results in demand for advanced architecture for networking. Application specific processors are used as a solution to increased demand , but the draw back with Application specific processors is it needs low power consumption, high performance and it is not flexible to changes when General purpose processors is used. it fails in debugging and difficulty in testing. Therefore to overcome the draw backs FPGA is used to design Domain specific processor. In this project Ethernet packet processor (EPP) is designed which acts as Domain specific process.EPP is used to generate frames for Analyzers, which can take the form of SoC. the generated frame is captured using Wireshark.
Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow, 2008
Our goal is to enable fast prototyping of networking hardware (e.g. modified Ethernet switches and IP routers) for teaching and research. To this end, we built and made available the NetFPGA platform. Starting from open-source reference designs, students and researchers create their designs in Verilog, and then download them to the NetFPGA board where they can process packets at line-rate for 4-ports of 1GE. The board is becoming widely used for teaching and research, and so it has become important to make it easy to re-use modules and designs. We have created a standard interface between modules, making it easier to plug modules together in pipelines, and to create new re-usable designs. In this paper we describe our modular design, and how we have used it to build several systems, including our IP router reference design and some extensions to it.
2000
As computer networks increase in speed, it becomes difficult to monitor and manage the transmitted digital content. To alleviate these problems, hardware-based search (FPgrep) and search-and-replace (FPsed) modules have been developed. FPgrep has the ability to scan packet payloads for a given set of regular expressions and pass or drop packets based on the payload contents. FPsed also scans packet payloads for a set of regular expressions and adds the ability to modify the payload if desired. The hardware circuits that implement the FPgrep and FPsed modules can be generated, compiled, and synthesized using a simple web interface. Once a module is created it is programmed into logic on a Field Programmable Gate Array (FPGA). The FPgrep and FPsed modules use FPGAs to process packets at the full rate of Gigabit-speed networks. Both modules, along with several supporting applications were developed and tested using the Field Programmable Port Extender (FPX) platform. Applications developed for the modules currently include a spam filter, virus protection, an information security filter, as well as a copyright enforcement function.
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Lecture Notes in Computer Science, 2004
Field Programmable Gate Arrays (FPGAs) can be used in Intrusion Prevention Systems (IPS) to inspect application data contained within network flows. An IPS operating on high-speed network traffic can be used to stop the propagation of Internet worms and to protect networks from Denial of Services (DoS) attacks. When used in the backbone of a core network, the device will be exposed to millions of active flows simultaneously. In order to protect the data in each connection, network devices will need to track the state of every flow. This must be done at multi-gigabit line rates without introducing significant delays. This paper describes a high performance TCP processing system called TCP-Processor which supports flow processing in high-speed networks utilizing multiple devices. This circuit provides stateful flow tracking, TCP stream reassembly, context storage, and flow manipulation services for applications which process TCP data streams. A simple client interface eases the complexities associated with processing TCP data streams. In addition, a set of encoding and decoding circuits has been developed which efficiently transports this interface between multiple FPGA devices. The circuit has been implemented in FPGA hardware and tested using live Internet traffic.