The Future Impact of GaAs Digital IC's (original) (raw)
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IEEE Transactions on Electron Devices, 1989
A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analogldigital LSIlVLSI integrated circuits is reported. A 4-bit analog-to-digital converter, a 2500-gate 8 X 8 multiplierlaccumulator and a 4500-gate 16 x 16 complex multiplier have been demonstrated using enhancement-mode (e-mode) nf -(AI, Ga) As/MODFET's, superlattice MODFET's, and doped channel heterostructure field-effect transistors (DCHFET), whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1-pm gate-length devices, direct-coupled FET logic (DCFL) ring oscillators, having realistic circuit structures, have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 pm of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysterisis less than 1 mV at room temperature. Fully functional 4-bit A-to-D circuits operating at frequencies up to 2 GHz were obtained. To our knowledge, these are the largest digital and mixed analogldigital circuits ever reported using MBE-grown LSI heterostructure FET technology.
Influence of MOSFET parameters on its parasitic capacitance and their impact in digital circuits
WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, 2007
Advanced development of technological processes influenced a wide use of MOSFET transistors in design of integrated digital circuits with high density packages (VLSI). However, in MOSFET transistors parasitic capacitances are present, which will influence on speed of operation in the circuits and dynamic dissipation power. The aim of this paper is to review the influence of channel dimensions, dimensions of source regions, dimensions of drain regions, concentration of impurity (doping concentration) in substrate, concentration of impurity in drain regions (source regions), concentration of impurity sidewalls, level of bias voltage values in particular parasitic capacitance values. Based on the results achieved actions will be determined in order to minimize parasitic capacitance that result in higher speed of operation and lower dynamic power dissipation. Decrease of region dimensions mentioned above depends on technological process capacity for minimal dimensions.
Experimental Evaluation of Gate Architecture Influence on DG SOI MOSFETs Performance
IEEE Transactions on Electron Devices, 2005
Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated. Index Terms-Double-gate (DG) transistor, gate misalignment, interface coupling, metal gate, MOSFETs, silicon-on-insulator (SOI) technology. I. INTRODUCTION S INCE bulk MOSFETs are expected to reach their limit for gate lengths below 30 nm [1], alternative architectures have been proposed to overcome their limitations [2]-[4]. The double-gate (DG) transistor is considered one of the most promising devices for extremely scaled CMOS technology generations [5]. Indeed, due to a good electrostatic control of the channel by the two gates, it is expected to provide smaller short-channel effects (SCE), near ideal subthreshold slopes and higher drive currents when compared to single-gate (SG) transistors [6], [7]. Among all the DG architectures, planar devices are promising: their process is closest to the bulk one, it is easy to cointegrate several architectures, and both gates Manuscript
IEEE , 2024
This paper investigates Gate-All-Around Field-Effect Transistors (GAA FETs) as viable solutions for modern low-power and high-performance electronic applications. Through extensive experimental analysis involving fabrication, electrical characterization, and simulation modeling, this study delves into the intrinsic electrical properties and performance metrics of GAA FETs. Key parameters such as threshold voltage, leakage current, sub-threshold swing, and transconductance are rigorously examined to assess the transistor's operational efficiency for low-power applications. Additionally, advanced simulation models are developed and validated to accurately predict GAA FET behavior, facilitating future design enhancements for high-performance computing. The findings underscore the advantageous features of GAA FETs, positioning them as promising candidates for fulfilling the requirements of both low-power consumption and high-performance computing. This research establishes a foundation for leveraging GAA FET technology in the development of innovative electronic devices, thereby opening avenues for diverse applications across various technological domains.
Moore's law lives on [CMOS transistors]
IEEE Circuits and Devices Magazine, 2003
he rapid growth of the electronics industry is based on the evolution of integrated-circuit (IC) technology to provide improvements in cost per function as well as performance. Technological advancements have been achieved over the past three decades primarily through the scale-down of device dimensions [1], [2], [3] in order to attain continued improvement in circuit speed and reduction in size (for lower unit manufacturing cost). The most important and fundamental building block of very-largescale-integrated (VLSI) circuits today is the metal-oxide-semiconductor field-effect transistor (MOSFET). Ideally, a MOSFET has high drive current (when the gate electrode is biased to turn the transistor on) and low leakage current (when the gate electrode is biased to turn the transistor off). As the MOSFET channel length is reduced to 50 nm and below, the suppression of off-state leakage current becomes an increasingly difficult technological challenge-one that will ultimately limit the scalability of the conventional MOSFET structure. This article reviews recent research performed at the University of California at Berkeley on advanced transistor structures that can extend the limit of device scaling to below 10 nm for future generations of MOS technology.
Device scaling limits of Si MOSFETs and their application dependencies
Proceedings of The IEEE, 2001
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications. technology development group, Essex Junction, VT, to work on 1-Mb DRAM, and then began work on sub-half-micron MOSFETs for logic in 1984. He has contributed to numerous high-speed CMOS projects from 1.0-m to 0.1-m scales. He invented on 32 U.S. patents in the areas of CMOS circuits, devices and processes, and has authored numerous papers in these areas. He is currently engaged in the pursuit of sub-one-volt device designs and continues work on high-speed CMOS device design.
Complementary heterostructure FET technology for low power, high speed, digital applications
1996
This paper describes a CMOS-like readout technology using GaAs heterostructure field effect transistors. Bandgap engineering techniques are described which provide complementaiy p-channel and n-channel GaAs FETs attractive for performing advanced signal processing functions with minimal power consumption and with precision operation in harsh environments. At 77 K, n&p channel CHFETs exhibit amplification ftors of 6.7 and 2.3 mA/V2, respectively, with nearly ideal sub-threshold characteristics and no I-V kinks or hysteresis. CHFET ring oscillators at 77 K attain propagation delays under 200 pS/gate while maintaining standby power dissipation under 1 iW/gate and switching power of0.1 W/gatefMHz. A simple operational amplifier exhibited 100 dB open loop gain at 65 K with 80 pA input leakage and 500 j.LW total power consumption.