Placement and Floorplanning in Dynamically Reconfigurable FPGAs (original) (raw)

Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems

2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Within this paper we present a floorplanner for partially-reconfigurable FPGAs that allow the designer to consider bitstream relocation constraints during the design of the system. The presented approach is an extension of our previous work on floorplanning based on a Mixed-Integer Linear Programming (MILP) formulation, thus allowing the designer to optimize a set of different metrics within a user defined objective function while considering preferences related directly to relocation capabilities. Experimental results show that the presented approach is able to reserve multiple free areas for a reconfigurable region with a small impact on the solution cost in terms of wire length and size of the configuration data.

Floorplanning for Partially Reconfigurable FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

Partial reconfiguration on heterogeneous fieldprogrammable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.

Optimized Placement Approach on Reconfigurable FPGA

International Journal of Modeling and Optimization

Adaptive systems based on Field-Programmable Gate Array (FPGA) architectures can benefit from the high degree of flexibility offered by Dynamic Partial Reconfiguration (DPR). In DPR, hardware modules composing an application can be allocated on demand or depending on a dynamically changing system. However, founders DPR tools are limited in functionality because it does not support an automatic placement , and require a manual inputs from the design. Manual placement not allows an efficient placement. The placement step represents a critical step in DPR flow on FPGA. It is highly impact routability, timing and density, hence performance of the system. In this paper, we present a novel placement algorithm to address these constraints by offering minimal fragmentation that minimizes resource utilization and reduces the total wirelength. The selection of the Partial Reconfigurable Region (PRR) is based on the shapes, location and communication with others. The proposed approach has been experimentally evaluated with a case study. Experimental results show the effectiveness of the proposed algorithm in the terms of exploration area and communication cost.

An Algorithm for Dynamically Reconfigurable FPGA Placement

International Conference on Computer Design, 2001

In this paper, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2%, 27.0%, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method

PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems

24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Partial reconfiguration (PR) is gaining more attention from the research community because of its flexibility in dynamically changing some parts of the system at runtime. However , the current PR tools need the designer's involvement in manually specifying the shapes and locations for the PR regions (PRRs). It requires not only deep knowledge of the FPGA device, the system architecture, but also many trial-and-error attempts to find the best-possible floorplan. Therefore, many research works have been conducted to propose automatic floorplanners for PR systems. However, one of the most significant limitations of those works is that they only consider the PRRs and ignore all other static modules. In this paper, we propose a novel PR floorplanner called PRFloor. It takes into account all components in the system. The main ideas behind PRFloor are the unique re-cursive pseudo-bipartitioning heuristic using a new, simple, yet effective Nonlinear Integer Programming-based biparti-tioner. The PRFloor performs very well in the experiments with various synthetic PR system setups with up to 130 modules, 24 PRRs and 85% of the FPGA resource. The average maximum clock frequency obtained for the actual PR systems implemented using PRFloor is even 3% higher than the similar systems without PR capability.

Performance-driven placement for dynamically reconfigurable FPGAs

ACM Transactions on Design Automation of Electronic Systems, 2002

In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.

Hardware module placement for dynamically reconfigurable architecture

Partial Reconfigurable FPGAs (Field Programmable Gate Array) allow tasks to be placed and removed dynamically at runtime. One of the challenging problems is the placement of modules on reconfigurable resources. Several modules placement techniques have been introduced in the literature to solve the temporal placement problem. This paper presents a temporal placement approach that manages the resources of a reconfigurable device. In fact, the authors' contribution focuses on introducing a new temporal placement algorithm that aims to minimize the communication cost between modules. Results show an important improvement in communication cost compared with other approaches.

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Self Reconfigurable Systems are completely independent in their management, thus they have the need to internally host reconfiguration management functionalities, such as core allocation, and to store or be able to autonomously obtain configuration bitstreams when needed. Within this scenario, the final system also needs to be able to autonomously perform choices relative to its internal management during computation; this requires, in particular, an internal solution for core allocation management, which includes maintaining information on the reconfigurable fabric state and being able to choose where to place new cores upon their arrival. We refer to these two aspects with the terms Empty Space Management and Online Placement Policy and to the global problem with the term Online Core Allocation Management. This paper presents a solution able to combine the online placement of cores with the runtime bitstreams relocation to implement a complete solution that can be used in conjunction with the runtime self reconfiguration. The validation phase presents the results obtained in placement management and relocation, compared to the results obtained by the state of art solutions to this problem.

SELECTIVE FITTING STRATEGY BASED REAL TIME PLACEMENT ALGORITHM FOR DYNAMICALLY RECONFIGURABLE FPGAs

Engineers in the field of Advanced computing paradigm struggles to satisfy the demand of high performance applications in terms of speed such as image processing, embedded computing ,video stream processing etc.,. Providing high speed in terms of truly multitasking of reconfigurable computing devices such as FPGAs acts as suitable computing platform for such applications. Two main problems in FPGA to fulfil the requirement are scheduling and placement of incoming hardware tasks. Scheduling and placement are the two process that depends on each other. Improper scheduling affects the placement performance. To the above two things, one more factor called fragmentation related closely that affects performance of FPGAs during placement. The performance metric used in this paper is task rejection ratio. Effective placement algorithm results minimum task rejection ratio. In this paper, we address the problem of real time scheduling and placement of hardware tasks by considering the factor called fragmentation in the objective to minimize the task rejection ratio. We developed an Selective fitting strategy based algorithm and simulation is carried out. Results are compared with basic placement fitting strategy such as first fit, best fit and worst fit. Our algorithm shows better performance in term of task rejection ratio.

Architecture-Adaptive Routability-Driven Placement for FPGAs

2005

Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates is limited adaptability. A placement algorithm that is targeted to a class of architecturally similar FPGAs may not be easily adapted to other architectures. The subject of this paper is the development of a routability-driven architecture adaptive FPGA placement algorithm called Independence. The core of the Independence algorithm is a simultaneous placeand-route approach that tightly couples a simulated annealing placement algorithm with an architecture adaptive FPGA router (Pathfinder). The results of our experiments demonstrate Independence's adaptability to island-style FPGAs, a hierarchical FPGA architecture (HSRA), and a coarse-grained reconfigurable architecture (RaPiD). The quality of the placements produced by Independence is within 1.2% of the quality of VPR's placements, 17% better than the placements produced by HSRA's placer, and within 0.7% of RaPiD' s placer. Further, our results show that Independence produces clearly superior placements on routing-poor island-style FPGA architectures.