Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK (original) (raw)

Matlab Toolbox for RF Receiver Modeling

Advanced Engineering Forum, 2013

In this paper a novel RF receiver modeling approach is presented. The novelty consists in the usage of the object oriented programming instead of the usual imperative programming. Classes were defined for entities as signal, non-ideality and RF/analog block, in order to achieve a basic RF receiver model. The main circuit non-idealities were identified, non-ideality parameters and their analytical models were encapsulated into classes. The effectiveness of the proposed modeling approach was demonstrated by developing in MATLAB a fairly complete model of a direct conversion receiver.

Matlab Modeling of Zero-IF Radio Receivers by Using Object Oriented Programming

This paper presents a novel approach to the modeling of radio receivers, based on object-oriented programming in Matlab. The RF/analog blocks are represented by analytical models, obtained by selecting, configuring and merging of pre-defined attributes; these attributes are closed-form analytical expressions of the basic analog signal-processing functions (signal amplification and filtering, frequency conversion, analog-to-digital conversion, etc.) and the non-idealities considered (noise, nonlinearity, carrier frequency offset, I/Q imbalance, etc.). This method enables the development of wellstructured yet fully scalable and re-configurable models, which are easy to maintain and refine further, by adding new features. A framework for modeling OFDM receivers was developed using this method; it comprises OFDM signal generators and accurate representations of the operations performed in digital baseband, from digital channel filtering to error correction and OFDM decoding. Also, several signal quality monitors such as the Signal to Undesired-Signal Ratio (SUSR) and Signal-to-noise and distortion ratio (SINAD) were implemented. The usefulness and flexibility of the proposed approach is demonstrated by an example, the modeling and analysis of a DVB-H tuner for both passband and equivalent baseband simulations.

IJERT-Design and Simulation of RF Receiver for LTE

International Journal of Engineering Research and Technology (IJERT), 2018

https://www.ijert.org/design-and-simulation-of-rf-receiver-for-lte https://www.ijert.org/research/design-and-simulation-of-rf-receiver-for-lte-IJERTCONV6IS13006.pdf RF front-end architecture plays a very vital role in a transceiver system. The design should be such that it provides a better noise figure and gain and good rejection to image frequencies and undesired noise. The purpose of this paper is to design receiver architecture for a long term evolution (LTE) base station for band 28 having an uplink of frequency of 703MHz to 748MHz. The conceptualised design of the receiver chain is to meet the various standards of 3GPP such as Receiver sensitivity, Noise figure and Gain. Choosing of proper components for meeting the requirements of both cost effective as well as performance enhancement is necessary. The schematic design of the receiver chain is drawn and is simulated using software tool NI-AWR for VSS simulations. The obtained simulated values provide us with the noise figure, gain, P1 dB, IIP3 and signal power.

RF COMPONENTS MODELING AND ANALYSIS

RF Passive components are used in the design of RF blocks as well as in system level integration. The efficient and accurate analysis of these components is required in order to meet the RF block or system level performances. I had studied the modeling of RF passive components for fast analysis approaches I had studied and developed a prototype design to simulate RF circuits in Pspice. The aim was to develop a functionality to simulate a RF block in spice simulator. Following issues were considered in this simulation i. S-parameter file compatibility with spice simulator ii. Synthesis and analysis of matching circuits iii. Modeling of passive components S-parameter file compatibility with spice simulator: For the circuit design I had considered system level LNA block and made it compatible with spice format The S-parameter file for LNA was not directly compatible with the spice format. An approach was investigated and a translator was developed to make it spice compatible. Hence a generalized code for Nport S-parameter file conversion to spice format was developed.

CAD for RF circuits

2001

Wireless transceivers for digital telecommunications are heterogeneous systems that combine digital hardware, software and analog circuitry. The pressure to miniaturization and lower power consumption for these transceivers imposes tight specifications on their analog RF parts. Many aspects of RF circuits cannot be simulated accurately and efficiently with a classical circuit-level SPICE approach. In this paper three important simulation problems for RF circuits are addressed: 1. high-level simulation of analog and RF blocks for the determination of the specifications of the circuits 2. accurate circuit-level simulation of nonlinear circuits with time constants that differ largely, 3. efficient and accurate computation of phase noise in RF oscillators For each of these problems, solutions are proposed. These solutions illustrate that accurate and efficient simulations of RF communication circuits need a heterogeneous variety of advanced algorithms.

Generation of multicarrier complex lowpass models of RF ICs

2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157)

The design of transceivers for wireless digital telecommunications is subject to severe requirements on cost and power consumption. This is a challenge for the design of RF front-end blocks that degrade the bit-errorrate of a telecommunication link. This paper describes a technique to generate accurate high-level models for the RF front-end blocks. The models take into account the nonlinear behavior as a function of frequency. The accuracy of the models is higher than classical complex equivalent models since out-of-band distortion is taken into account. The technique, that is verified with a low-noise amplifier design for 5 GHz WLAN, yields an important gain in simulation efficiency of RF ICs, compared to circuit-level simulations.

Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end

IEEE Circuits and Systems Magazine, 2006

The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure. This paper addresses both the architecture and the circuits for the RF front-end of a terminal with cellular (GSM, EDGE and UMTS), LAN (IEEE802.11a/b/g) and Bluetooth radio interfaces. A multi-standard simulator has been developed to validate the architectural and design choices in terms of error rates at bit or packet level. The simulator takes into account implementation non-idealities and performs all tests to be passed to comply with the given standards. It also hints at the need for implementation margins as well as at possible optimization between different RF-blocks. The final solution, still under design, will consists of two chips, one including the TX and the other the RX for all the above standards. The cellular (plus Blue-tooth) transmitter relies on a Linear amplification with Non-linear Component (LINC) architecture that uses direct modulation of the carrier. This allows power saving because DAC and up-conversion mixers are not required. The WLAN (plus Blue-Tooth) transmitter adopts a direct-conversion architecture that implements an internal output matching over all the frequency bands while maintaining good system efficiency. The same building blocks are used for all standards, saving power and chip area. The cellular receiver architecture is able to reconfigure between Low-IF for GSM and direct conversion for UMTS and Blue-tooth. The key aspects in achieving the specs in a fully integrated fashion are a mixer with a very high dynamic range, a careful control of DC offsets and a highly tunable VCO. The WLAN receiver also uses direct-conversion with a Low Noise Amplifier based on a common gate topology that uses positive feedback through integrated transformers to improve input matching and noise. The frequency down-converter uses current driven passive mixers to achieve low 1/f noise corner, and high linearity with low power consumption. Finally, the base-band blocks can be shared among all the standard, thanks to their high reconfigurability. The paper describes the ideas behind the key RF blocks and some details of circuit implementation. Experimental measurements from sub-blocks in a 0.13 µm CMOS technology are presented and discussed.

Automated Receiver Design and Optimization for 4G Wireless Communication Systems

2006 IEEE International Behavioral Modeling and Simulation Workshop, 2006

This paper presents the design methodology and underlying algorithms of a tool developed for automated receiver design and optimization for fourth generation (4G) Wireless Communication Systems. An algorithm to systematically design and optimize the receiver budget for the multi-standard case is introduced. The goal of this algorithm is to find a multistandard receiver budget that meets or exceeds the specs of the addressed wireless standards while keeping the requirements of each of the receiver blocks as relaxed as possible. This tool offers RF engineers a deep insight into the receiver behavior at a very early stage of the design flow. It models the impact of some circuit non-idealities using a high level of abstraction. This reduces the number of design iterations and, thus, the time-to-market of the solution. The reuse of already available intellectual property (IP) blocks is also considered in the tool. This can result in a significant cost reduction of the receiver implementation.

AN ANALYSIS OF CMOS RE-CONFIGURABLE MULTI- STANDARD RADIO RECEIVERS BUILDING BLOCKS CORE

Revue Roumaine des Sciences Techniques - Serie Électrotechnique et Énergétique

This paper presents the analysis of CMOS re-configurable multi-standard radio receivers building blocks core. The paper's main goal is to determine the building blocks key parameters, like gain, noise figure (NF) and third order intercept point (IP3) and to link them to the receiver overall performance. An overview of existing circuit topologies is presented. The analysis emphasizes the solutions that fit best a true re-configurable multi-standard implementation.