A single-chip digitally calibrated 5.15~5.825GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN (original) (raw)

ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2 20.2 A Digitally Calibrated 5.15 - 5.825GHz Transceiver for 802.11a Wireless LANs in 0.18μm CMOS

2009

Although attractive as a highly integrated solution, direct conversion architecture suffers from problems such as DC offsets, flicker noise and poor quadrature matching, that are further aggravated by using CMOS technology [1]. Furthermore, the 802.11a standard high bit-rate modes require closely matched I/Q frequency response. To alleviate those limitations, a transceiver topology allowing the use of the companion digital chip for calibration, has been implemented as shown in Fig. 20.2.1. Both transmitter and receiver use direct conversion and employ fully differential signal paths. By adding loop-back switches, the DC offset, TX and RX I/Q gain mismatch and I/Q frequency response can be independently calculated and corrected during the idle time between frames or at power-up.

A single-chip, 5.15GHz5.35GHz, 2.4GHz2.5GHz, 0.18μm CMOS RF transceiver for 802.11a/b/g wireless LAN

2003

A dual band, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, zero-IF transceiver is fabricated on a 0.18/spl mu/m CMOS process. The fully integrated synthesizer and VCO achieve an integrated phase error of 0.8/spl deg/ at 5GHz. The transmitter achieves -33dB EVM, while the receiver features a 5.2dB noise figure (NF) at 5.25GHz and 3.5dB NF at 2.45GHz. An architecture including feedback paths enables digital calibration, which help eliminate I/Q mismatch and achieve accurately matched baseband filter tuning.

A fully integrated CMOS low noise amplifier for IEEE 802.11a standard applications

2011

In this paper, a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18μm CMOS technology for IEEE 802.11a applications is presented. Using cascode topology and modified input impedance network as well as inductor neutralization technique, the LNA power dissipation is lowered to 16mW while having power gain of 17.82dB and reverse isolation factor of -58.37dB at centre frequency of 5.5GHz. S11 and S22 are equal to -16.1dB and -32dB, respectively. Designed LNA has IIP3 of +3dBm and less than 2.9dB noise figure (NF) in working band width, as resulted from transistor level simulation using TSMC RF CMOS 0.18 μm design kit.