Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems (original) (raw)
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Scalable Interconnection and Integration of Nanowire Devices without Registration
Nano Letters, 2004
A general strategy for the parallel and scalable integration of nanowire devices over large areas without the need to register individual nanowire−electrode interconnects has been developed. The approach was implemented using a Langmuir−Blodgett method to organize nanowires with controlled alignment and spacing over large areas and photolithography to define interconnects. Centimeter-scale arrays containing thousands of single silicon nanowire field-effect transistors were fabricated in this way and were shown to exhibit both high performance with unprecedented reproducibility and scalability to at least the 100-nm level. Moreover, scalable device characteristics were demonstrated by interconnecting a controlled number of nanowires per transistor in "pixel-like" device arrays. The general applicability of this approach to other nanowire and nanotube building blocks could enable the assembly, interconnection, and integration of a broad range of functional nanosystems.
Photolithographic Approaches for Fabricating Highly Ordered Nanopatterned Arrays
Nanoscale Research Letters, 2008
In this work, we report that large area metal nanowire and polymer nanotube arrays were successfully patterned by photolithographic approach using anodic aluminum oxide (AAO) templates. Nanowires were produced by electrochemical deposition, and nanotubes by solution-wetting. The highly ordered patterns of nanowire and nanotube arrays were observed using scanning electron microscopy (SEM) and found to stand free on the substrate. The method is expected to play an important role in the application of microdevices in the future.
Wafer-Scale Assembly of Highly Ordered Semiconductor Nanowire Arrays by Contact Printing
Nano Letters, 2008
been one of the significant bottleneck challenges facing the potential integration of nanowires for both nano and macro electronic circuit applications. Many efforts have focused on tackling this challenge, and while significant progress has been made, still most presented approaches lack either the desired controllability in the positioning of nanowires or the needed uniformity over large scales. Here, we demonstrate wafer-scale assembly of highly ordered, dense, and regular arrays of NWs with high uniformity and reproducibility through a simple contact printing process. We demonstrate contact printing as a versatile strategy for direct transfer and controlled positioning of various NW materials into complex structural configurations on substrates. The assembled NW pitch is shown to be readily modulated through the surface chemical treatment of the receiver substrate, with the highest density approaching ~8 NW/µm, ~95% directional alignment and wafer-scale uniformity. Furthermore, we demonstrate that our printing approach enables large-scale integration of NW arrays for various device structures on both Si and plastic substrates, with a controlled semiconductor channel width, and therefore ON current, ranging from a single NW (~10 nm) and up to ~250 µm, consisting of a parallel array of over 1,250 NWs.
Self-integration of nanowires into circuits via guided growth
Proceedings of the National Academy of Sciences, 2013
The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom-up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel "self-integration" of NWs into electronic circuits and functional systems based on guided growth. nanotechnology | nanolithography | self-assembly | nanoelectronics | 1D nanostructures T he sustained progress in semiconductor technology introduces new challenges associated with the scaling and functionality of nanosize components. In the face of these challenges, alternative unconventional device and fabrication concepts based on bottom-up assembly of synthetic nanostructures are being intensively explored (1). These nanostructures, such as quantum dots (2), nanotubes (3), and nanowires (NWs) (4), can be chemically synthesized with exquisite control over their structures and properties down to the atomic level. On the other hand, their self-assembly alone is unlikely to produce the arbitrary geometries and long-range order that are required for their integration into functional systems. To realize such systems, bottomup assembly may be used as a complementary step in a sequence of top-down fabrication processes. Such a hybrid top-down/ bottom-up approach can be based on the directed self-assembly of building blocks onto a lithographically produced template to fit the design of an integrated functional system. Thus, the building blocks integrate themselves into the system, as one of the layers in the overall design. Here we demonstrate the feasibility of this "self-integration" concept with the parallel fabrication of large numbers of devices and complex circuits, based on guided growth of horizontal NWs (5).
Knocking Down Highly-Ordered Large-Scale Nanowire Arrays
Nano Letters, 2010
The large-scale assembly of nanowire elements with controlled and uniform orientation and density at spatially welldefined locations on solid substrates presents one of the most significant challenges facing their integration in real-world electronic applications. Here, we present the universal "knocking-down" approach, based on the controlled in-place planarization of nanowire elements, for the formation of large-scale ordered nanowire arrays. The controlled planarization of the nanowires is achieved by the use of an appropriate elastomer-covered rigid-roller device. After being knocked down, each nanowire in the array can be easily addressed electrically, by a simple single photolithographic step, to yield a large number of nanoelectrical devices with an unprecedented high-fidelity rate. The approach allows controlling, in only two simple steps, all possible array parameters, that is, nanowire dimensions, chemical composition, orientation, and density. The resulting knocked-down arrays can be further used for the creation of massive nanoelectronic-device arrays. More than million devices were already fabricated with yields over 98% on substrate areas of up, but not limited to, to 10 cm 2 .
Facile Integration of Ordered Nanowires in Functional Devices
The integration of one dimensional (1D) nanostructures of non-industry-standard semiconductors in functional devices following bottom-up approaches is still an open challenge that hampers the exploitation of all their potential. Here, we present a simple approach to integrate metal oxide nanowires in electronic devices based on controlled dielectrophoretic positioning together with proof of concept devices that corroborate their functionality. The method is flexible enough to manipulate nanowires of different sizes and compositions exclusively using macroscopic solution-based techniques in conventional electrode designs. Our results show that fully functional devices, which display all the advantages of single-nanowire gas sensors, photodetectors, and even field-effect transistors, are thus obtained right after a direct assembly step without subsequent metallization processing. This paves the way to low cost, high throughput manufacturing of general-purpose electronic devices based on non-conventional and high quality 1D nanostructures driving up many options for high performance and new low energy consumption devices.
Toward the Development of Printable Nanowire Electronics and Sensors
Advanced Materials, 2009
REVIEW www.advmat.de approaches, which rely on the packing of the atoms/molecules along energetically preferential directions. As a result, the grown materials have high crystallinity, which often renders them with superb electrical and optical properties. Specifically, semiconductor NWs are considered as promising materials due to their well-developed synthesis processes and the ability to tailor material properties through shape, size, and atomic-composition control. The as-grown NW materials, however, have random alignment and orientation, unless epitaxial growth is used to enable vertically aligned NW arrays. Therefore, developing routes for large-scale assembly of NWs on desired support substrates is needed to further broaden the application spectrum through a hybrid strategy utilizing the ''bottom-up'' semiconductor materials growth processes with the ''top-down'' device-fabrication processes.
Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics
Nano Letters, 2007
We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW fieldeffect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.
Journal of Materials Chemistry, 2009
Inorganic nanowire-based devices have recently drawn extensive attention as one of the nextgeneration device architectures. Nevertheless, a lack of mass-production methods has been one of the major hurdles holding back the practical applications of such devices. Herein, we review three promising strategies for the massive assembly of inorganic nanowires for their device applications, which are topically selected: selective growth, selective assembly, and direct printing methods. The advantages and disadvantages of these methods are also discussed.