Feasibility exploration of partial Reconfigurable FPGA for REAL products (original) (raw)

High-level design flow and environment for FPGA-based dynamic partial reconfiguration

International Journal of Electronics, 2017

High-level design flow and environment for FPGA-based dynamic partial reconfiguration The main motivation of this paper is related to the lack of a high-level design flow for a partial dynamic reconfiguration management. Our contribution consists in proposing a high-level add-on methodology to the Xilinx's design flow for a dynamic partial reconfiguration. The main objective is to give an abstract view of the developed application in order to facilitate the designer task. The suggested design flow offers an application centric view on dynamic reconfiguration designs, which permits simplifying the optimization and generation of such designs. A new formulation of the reconfigurable modules' mapping process is put forward. This allows a design space exploration so as to find the convenient number of reconfigurable regions and their sizes as well as the reconfiguration sequence. A new tool was proposed to support our methodology by allowing creating and synthesizing graphical models of the developed application. We introduce a new block diagram to represent this latter and a sequence model that can be used for the design optimizations. To validate the proposed dynamic-partial-reconfiguration design environment, two application examples are given at the end of the paper. They demonstrate the usefulness of the suggested models and methods.

Remote and Partial Reconfiguration of FPGAs: tools and trends

Parallel and …, 2003

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. This paper has three main goals. The first one is to present the trend of DRS, highlighting the problems and solutions of each DRS generation. The second goal is to present in detail the configuration architecture of a commercial FPGA family allowing DRS implementation. The last goal is to present a set of tools for remote and partial reconfiguration developed for this FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs.

Support for partial run-time reconfiguration of platform FPGAs

Journal of Systems Architecture, 2006

Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support.

Exploring the self reconfiguration of FPGA: design flow, architecture and performance

International Journal, 2011

Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. Partial Reconfigurable FPGAs allow tasks to be placed and removed dynamically at runtime. These reconfigurable systems have a 2-layer hardware and software architecture that permits a variety of different interfaces. Further, these systems enable self-reconfiguration under software control through a reconfiguration hardware interface called Internal Configuration Access Port (ICAP). In this paper, experiments are conducted in order to evaluate the design complexity and reconfiguration latency of self reconfiguration. The results show that the main goal of self reconfiguration is to shorten the reconfiguration time while not degrading the performance of the final design.

Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model

Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real experiments we produce a cost model of Partial Reconfiguration (PR). This model is introduced to calculate the expected reconfiguration time and throughput. In order to develop a realistic model we take into account all the physical components that participate in the reconfiguration process. We analyze the parameters that affect the generality of the model and the adjustments needed per system for error-free evaluation. We verify it with real measurements, and then we employ it to evaluate existing systems presented in previous publications. The percentage error of the cost model when comparing its results with the actual values of those publications varies from 36% to 63%, whereas existing works report differences up to two orders of magnitude. Present work enables a user to evaluate PR and decide whether it is suitable for a certain application prior entering the complex PR design flow.

FPGA Architectures for Reconfigurable Computing

To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs...

A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board

2015

During recent years much research focused on making Partial Reconfiguration (PR) more widespread. The FASTER project aimed at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework lies in the use of partial dynamic reconfiguration seen as a first class citizen throughout the entire design flow in order to exploit FPGA device potential. The STMicroelectronics SPEAr development platform combines an ARM processor alongside with a Virtex-5 FPGA daughter-board. While partial reconfiguration in the attached board was considered as feasible from the beginning, there was no full implementation of a hardware architecture using PR. This work describes our efforts to exploit PR on the SPEAr prototyping embedded platform. The paper discusses the implemented architecture, as well as the integration of Run-Time System Manager for scheduling (run-time reconfiogurab...

Communication Architectures for Dynamically Reconfigurable FPGA Designs

2007 IEEE International Parallel and Distributed Processing Symposium, 2007

This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set ofparameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated. The analysis takes a minimal communication system for connecting four hardware modules as a common basis for the comparison of the diverse data given in the papers on the different architectures.

Exploiting dynamic reconfiguration of platform FPGAs: implementation issues

International Parallel and Distributed Processing Symposium/International Parallel Processing Symposium, 2006

The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing

Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems

Iet Computers and Digital Techniques, 2007

This paper describes a tool that creates partiallyreconfigurable modules from the bitstreams of individual component modules. The resulting modules are intended for use in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically-reconfigurable platform FPGAs. The corresponding design flow is described together with a basic run-time support system.