A new multilevel DC-AC converter topology with reduced switch using multicarrier sinusoidal pulse width modulation (original) (raw)
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A New Simplified Multilevel Inverter Topology for DC–AC Conversion
IEEE Transactions on Power Electronics, 2006
Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity. Theoretical predictions are validated using simulation in SPICE, and satisfactory circuit operation is proved with experimental tests performed on a laboratory prototype. Index Terms-Capacitor clamped, diode clamped, field programmable gate array (FPGA), H-bridge, multilevel inverter.
A New Simplified Multilevel Inverter Topology for DC–AC Conversion
IEEE Transactions on Power Electronics, 2000
Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity. Theoretical predictions are validated using simulation in SPICE, and satisfactory circuit operation is proved with experimental tests performed on a laboratory prototype. Index Terms-Capacitor clamped, diode clamped, field programmable gate array (FPGA), H-bridge, multilevel inverter.
TELKOMNIKA, 2023
In this proposed paper, multicarrier sinusoidal pulse width modulation (M-SPWM) method is implemented for design of 15 level reduced switches inverter topology. This inverter topology generates 15 level output-voltage with suitablelswitching pulse production using M-SPWM and altered level of voltages are attained with distinction of modulationlindex. The split inductor is used to diminish the harmoniclcontent and flatted output current. This type of system which contains different range of different range of voltage supplies. As a result, this inverter reduces the difficulty in gating time calculation and there is no neutral point fluctuation issue. This paper illuminates the modes of switching and minimization of stress in voltage and harmonic diminution are examined. The grades of the projected multilevel inverter (MLI) system are verified using Matlab/Simulink and dsPIC controller respectively.
A novel multilevel inverter with reduced components and minimized voltage unbalance
International Journal of Power Electronics and Drive Systems, 2022
Multilevel inverters are an emerging area of research in the field of power electronic circuits and applications. It has many advantages like near-sinusoidal output voltage, lower total harmonic distortion (THD), reduced dv/dt stress, lower peak inverse voltage (PIV) and so on. But there are some associated problems as well such as cost, size complexity, and capacitor unbalance voltage. Here a novel nine level inverter topology has been proposed which addresses the issue of high no of switching and capacitor voltage unbalance. The proposed system has numerous advantages. The cost, size and complexity are reduced and the voltage unbalance problem is solved. The voltage stress across the switches is also reduced. The power loss distribution among the switches is optimum. So, the efficiency of the system is improved. Hence the overall system performance is improved. The system performs well for varying load like resistive, inductive as well as motor load. The stator voltage speed control of a single-phase induction motor has also successfully been achieved. The pulse width modulation PWM technique has been used for producing the switching pulses. The complete simulation analysis of these systems has been realized using MATLAB software. A comparative analysis of this system with the recently proposed systems has been done which shows significant advantages in all the above mention areas.
International Journal of Power Electronics and Drive Systems, 2023
Multilevel inverters have the benefit of producing high output voltage values with little distortion. This paper deals with decreasing total harmonic distortion (THD) and providing an output voltage with various step levels switching devices. In this study, a 27-level inverter with three asymmetric H-Bridge was designed and simulated based on level shift sinusoidal pulsewidth modulation and phase shift sinusoidal pulse-width modulation methods. MATLAB/Simulink has been used to create this model and test it at different types of loads. The results showed that a multilevel inverter with (PS-PWM) produces less (THD) than a multilevel with (LS-PWM), when the resistive load was used, the produced voltage and current THD in (PSPWM) and (LS-PWM) are 3.02% and 4.30% respectively, that has resulted from the linearity between voltage and current in the resistive load. While in the case of applying an inductive load, the THD in the voltage is constant in both (PS-PWM) and (LS-PWM) methods and has the same values as the THD in a resistive load. However, the THD in the current with inductive load decreased to 2.79% in (PS-PWM) and 4.04% in (LS-PWM). Finally, these results show that the performance of the proposed power circuit with PS-PWM is better than (LS-PWM)
A Novel Multilevel Inverter with Reduced DC Sources
IJIREEICE, 2015
Multilevel inverters have become more popular in high power and high voltage application. They have a unique structure which makes it possible to reach high voltages with less harmonic content. Harmonic content of the output voltage waveform decreases as the number of output voltage level increases. The main advantages are lower Total Harmonic Distortion (THD), less stress on the power switches and higher efficiency. However, increase in the device count due to increased voltage levels makes the control method complex and hence expensive. This paper presents a nine level inverter with reduced DC sources which is capable of obtaining all additive and subtractive combinations of input DC levels. This topology requires less power switches compared to conventional multilevel inverter and less gate drives. The proposed topology is presented through a nine-level inverter with an appropriate modulation scheme and detailed simulation has been carried out in MATLAB/Simulink. A comparison is made between proposed topology and the conventional multilevel topology on the basis of device count, number of levels in the output voltage and THD.
Single Phase Multilevel Inverter By Using Sinusoidal Pulse Width Modulation Technique
2018
In this project, a novel multilevel inverter is proposed. The proposed multilevel inverter generates seven levels AC output voltage with the appropriate gate signals design. Also, the low pass filter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multi-level inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. By using resonant switching capacitor converter, the voltage balance of input capacitors is achieved. Sinusoidal pulse width modulation is used to control the multilevel inverter. IndexTerms – Multilevel inverter, Sinusoidal Pulse Width Modulation,
2014
This paper proposes a 7 level and 15 level unequal voltage sources Multilevel Inverter (MLI) using Degree Modulated Pulse Generator (DMPG) Technique. This technique presents a modulation time control switching for generating the pulse for multilevel inverter and requires n dc sources to obtain (2 n_ 1) output voltage level with a simple resistive load. This paper proposes a new concept of switching with reduced number of switches and batteries. There is comparison between 7 level and 15 level among output voltage and harmonic profile. Simulation work is observed by using the MATLAB/SIMULINK software which validated the proposed method and THD profiles are presented in FFT window.
— Multi-level inverter has been widely accepted for high voltage applications. Their performance is highly superior to that of conventional two level inverter due to reduced harmonic distortion, lower electromagnetic interference and higher dc link voltages. Multi-level inverter (MLI) has some disadvantages such as increased number of components, complex pulse width modulation control method, and voltage-balancing problem. In order to increase the level of the output, the numbers of switches are increased and losses and complexity also increased. Hence to reduce these losses and complexity, a new topology is designed in this project i.e. Multi-level inverter (MLI) with reduced number of switches. A new inverter topology has been proposed which has superior features over conventional topologies in terms of the required power switches and isolated dc supplies, control requirements and reliability. In the mentioned topology, the switching operation is separated into high-and low-frequency parts. Design and simulation analysis of new 7 level inverter topology with multicarrier spwm techniques is presented in this project thesis using MATLAB/SIMULINK
Five Level Hybrid Cascaded Multilevel Inverter Harmonic Reduced in PWM Switching Scheme
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as a inverter. This paper describes a harmonics reduced in a hybrid cascaded multilevel inverter circuit with pulse width modulation (PWM) scheme. These scheme pulse width modulations in modified method are uses reduce switching device. These methods are a conventional inverter and hybrid inverter combine form. This topology used the combined form of a new five level hybrid cascaded multilevel inverter. The multilevel carrier based pulse width modulation methods are used in this topology five level output voltage wave forms is shown in FFT window MATLABE/SIMULINK is used to simulate the inverter circuit operation and control signals.