Power Optimization in Domino Circuits using Stacked Transistors (original) (raw)

Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics

2006 International Conference on Microelectronics, 2006

In this paper, a new domino logic structure whose architecture is based on a leakage biased (LB) domino circuit is introduced. The proposed technique improves the performance and the dynamic power consumption of the circuits. In addition, the number of transistors is reduced leading to a lower silicon area. Simulations are done for various circuits. Compared to the LB method, in a full adder circuit, the delay is reduced more than 25%; also, the dynamic and the static powers have reduced slightly.

A LITERATURE SURVEY AND INVESTIGATION OF VARIOUS HIGH PERFORMANCE DOMINO LOGIC CIRCUITS

In deep sub-micron regions, the dynamic power and abstaining reliability problems will be reduced when the power supply voltage was trimmed down. The consumption of power in highly performing circuits has climbed to the level where it enforces the most important limitation to the rising performance and functionality. If power consumption is keep on increasing then the highly performing circuits will start to intake power in terms of more than thousands. The foremost factor in CMOS technology based design is dynamic switching power which can be reduced by reducing the supply voltage. If the supply voltage is reduced then it automatically reduced the transistor current which affects the speed of the circuit. The threshold voltages are scaled down so that it will compensate the speed of the circuit which was affected because of lowering the supply voltage. It also helps to maintain the dynamic power consumption with sufficient level without affecting the performance of the circuit. As a result of threshold voltage reduction the sub threshold leakage current starts increasing exponentially. It will be a tremendous boost in the designing of energy efficient circuits which was focusing on lowering the leakage current. The domino logic circuit design techniques are suitable for highly performing circuits for its higher speed and uniqueness of area in comparison with Static CMOS Circuits. The noise margin illustrates significant reduction if the domino logic circuits were operated in deep sub micrometer. In this paper, a literature survey and investigation of various domino logic circuits have been carried out stating their features, advantages and disadvantages in a profound manner.

A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting. This paper also analyses the PDP of the circuit at very low voltage and different W/L ratio of the transistors.

Speed and Noise Immunity Enhanced Low Power Dynamic Circuits

Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a standard domino circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

A low-power circuit technique for domino CMOS logic

Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipation with almost same noise immunity compared to the recently proposed circuit techniques for dynamic logic styles to improve noise immunity. The concept is validated through extensive simulation.

Energy efficient and high speed domino logic circuits

2015

Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.

Domino logic designs for high-performance and leakage-tolerant applications

Integration, 2013

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.

Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

2014

The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported...

Performance of low power Domino Circuits using pseudo dynamic buffer

IOSR Journal of VLSI and Signal Processing, 2014

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit for different logic function, loading condition, clock frequency and power supply. Our proposed circuit reduces power consumption and power delay product of the domino circuit as compare to other domino circuit proposed earlier. All the simulation result is carried out TSMC -0.18µm CMOS technology at 1.8V power supply.

Comparative Study of Leakage Reduction Techniques for Domino Logic Circuit

With the advancement of technology, size of transistor, supply voltage, gate oxide thickness has been decreased but the leakage in device has increased. Projecting these trends, it can be seen that the leakage power dissipation will equal to the active power dissipation within a few generations. Hence, efficient leakage power reduction methods are very critical for the deep-submicron and nanometer circuits. In this paper Lector based Footed Diode Domino Logic circuit technique is introduced for leakage reduction, which provides efficient reduction in leakage in ideal and non ideal mode of operation. In this technique a p-type and an n-type leakage control transistor (LCT) are introduced between the pull-up and pull-down network, and the gate of one is controlled by the source of the other. For any combination of inputs, one of the LCTs will operate near its cut-off region and will increase the resistance between supply voltage and ground, resulting in reduced leakage current.