Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection (original) (raw)

An Application-Specific Power Consumption Optimization for Wearable Electrocardiogram Devices

2022

This paper explores ways for energy consumption reduction in wearable and Remote Patient Monitoring (RPM) devices. We use the XBeats ECG patch as a case study application for remote Electrocardiogram (ECG) wearable device power consumption benchmarking. Systematic energy consumption profiling criteria is proposed for evaluating participating components in an RPM device. We isolate each hardware component to find power-intensive processes in the XBeats system, discover energy consumption patterns, and measure voltage, current, power, and energy consumption for a given time period. The proposed optimization techniques demonstrate significant improvements to the hardware components on the ECG patch. The results show that optimizing the data acquisition process saves 8.2% compared to the original power consumption and 1.62% in data transmission over BLE, thus extending the device lifetime. Lastly, we optimize the data logging operation to save 54% of data initially written to an external drive.

An Energy-Efficient Algorithm for Wearable Electrocardiogram Signal Processing in Ubiquitous Healthcare Applications

Sensors (Basel, Switzerland), 2018

Rapid progress and emerging trends in miniaturized medical devices have enabled the un-obtrusive monitoring of physiological signals and daily activities of everyone's life in a prominent and pervasive manner. Due to the power-constrained nature of conventional wearable sensor devices during ubiquitous sensing (US), energy-efficiency has become one of the highly demanding and debatable issues in healthcare. This paper develops a single chip-based wearable wireless electrocardiogram (ECG) monitoring system by adopting analog front end (AFE) chip model ADS1292R from Texas Instruments. The developed chip collects real-time ECG data with two adopted channels for continuous monitoring of human heart activity. Then, these two channels and the AFE are built into a right leg drive right leg drive (RLD) driver circuit with lead-off detection and medical graded test signal. Human ECG data was collected at 60 beats per minute (BPM) to 120 BPM with 60 Hz noise and considered throughout the ...

Ultra Low Power programmable biomedical SoC for on-body ECG and EEG processing

2010

An Ultra Low Power (ULP) biomedical System-on-Chip (SoC) has been developed for efficient ECG/EEG signal processing in a Body Area Network environment. This experimental SoC explores the use of event-driven peripheral modules that autonomously interact with external sensors together with the use of an Application-Specific-Instruction-set-Processor (ASIP) to optimize energy-efficiency during active and sleep periods. The SoC has been manufactured in standard 90nm CMOS process and use has been made of power gating to reduce leakage power that starts to become more dominant in advanced technologies. When running an ECG algorithm that is capable of reliably detecting the QRS complex in an ambulatory environment, an average power consumption of 10 μW has been measured at 0.7 V supply.

Low Power Optimisations for IoT Wearable Sensors Based on Evaluation of Nine QRS Detection Algorithms

IEEE Open Journal of Circuits and Systems, 2020

This paper aims to reduce the power consumption of electrocardiography based wearable healthcare devices, by introducing power reduction approaches and considerations at system level design, where we have the highest potential to influence power. It focuses, in particular, on algorithm design and implementation, data acquisition, and transmission under constrained resources. A thorough investigation of the suitability of nine existing algorithms for on-sensor QRS feature detection is conducted, with respect to metrics such as sensitivity, positive predictivity, power consumption, parameter choice and time delay. Optimisation of data acquisition on CPU-based IoT systems is performed, and the current consumption is reduced by a factor of 3 using a combination of direct memory access (DMA) list approach and low-level register manipulations for task delegation. The acquisition data rate, sampling rate, buffer and batch size are also optimised. To reduce the power consumption by data transmission, the effect of on-sensor versus off-sensor processing is investigated. While focusing on CPU-based systems with experiments performed on a generic low-power wearable platform, the design optimisation and considerations proposed in this work could be extended to custom designs and allow further investigation into QRS detection algorithm optimisation for wearable devices. INDEX TERMS Bluetooth low energy, direct memory access, Internet of Things, on-chip processing, QRS detection, wearable sensors.

IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities)

2012 IEEE 12th International Conference on Bioinformatics & Bioengineering (BIBE), 2012

The objective of the IcyHeart project is to investigate and demonstrate a highly integrated and power-efficient microelectronic solution for remote monitoring of a subject's electrocardiogram (ECG) signals. A complete System-on-a-Chip (SoC) is being developed that embarks on a single chip an ultralow-power signal acquisition front-end with analogue-to-digital converter (ADC) for ECG, a low-power digital signal processor (DSP) and a low-energy radio frequency (RF) transceiver. These features, for the first time, coexist on a single die. Energy efficient signal processing algorithms targeting ECG, and expandable to other bio-signals, are embedded and run on the on-chip DSP. The final IcyHeart product will consist of a tiny PCB embarking IcyHeart SoC and all the necessary discrete components and powering circuit. The outcome of the project is expected to generate high market value for the European SMEs developing novel cardio-monitoring products in home and professional environments, and to create high societal impact for several categories of European citizens requiring miniature, comfortable and easy-to-use wireless tele-healthcare solutions.

Rapid processor customization for design optimization: A case study of ECG R-peak detection

2011 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2011

In engineering wireless body area network platforms it is crucial to meet performance goals at minimal hardware cost and energy required. This paper describes a design flow that relies on processor customization of Tensilica's Xtensa processor cores. We introduce custom instructions to expedite wavelet processing used in an ECG R-peak detection application. We explore several instruction extensions and show that customized processor cores significantly reduce program execution time and energy requirements for this application.

Hardware-in-the-loop simulation and energy optimization of cardiac pacemakers

Implantable cardiac pacemakers are medical devices that can monitor and correct abnormal heart rhythms. To provide the necessary safety assurance for pacemaker software, both testing and verification of the code, as well as testing the entire pacemaker hardware in the loop, is necessary. In this paper, we present a hardware testbed that enables detailed hardware-in-the-loop simulation and energy optimisation of pacemaker algorithms with respect to a heart model. Both the heart and the pacemaker models are encoded in Simulink/Stateflow™ and translated into executable code, with the pacemaker executed directly on the microcontroller. We evaluate the usefulness of the testbed by developing a parameter synthesis algorithm which optimises the timing parameters based on power measurements acquired in real-time. The experiments performed on real measurements successfully demonstrate that the testbed is capable of energy minimisation in real-time and obtains safe pacemaker timing parameters.

A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis: ECG Prototype Architectural Design Space Exploration

2008

In this paper we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart Electrocardiogram (ECG) real-time analysis as a Hardware/Software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant bio-medical application, with good potential market since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW co-design. We investigate a symmetric multi-processor architecture based on STMicroelectronics VLIW DSPs that process in real-time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real-time, even with high sampling frequencies, and ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with...

Design and Implementation of Robust Low Power ECG Pre-processing Module

IETE Journal of Research, 2020

A robust low power Electrocardiogram (ECG) pre-processor is proposed to extract the useful information from biomedical signal. The methodology uses window-based efficient design that consumes less power and resources of Field Programmable Gate Array (FPGA). The comparison has been done among different window functions and filter architectures (Symmetric and Anti-symmetric). The entire hardware implementation is carried out on ZedBoard Zynq-7000 FPGA board. The inference has been drawn that symmetric Bartlett window consumes only 0.88%, 5.13%, and 9% of LUTs, slice registers and DSPs units respectively. 35mW of dynamic and 105 mW of static power is consumed by the pre-processor module. The proposed design is recommended to find applications in wearable and portable biomedical equipments.