Built-in jitter test schemes for mixed-signal integrated circuits (original) (raw)

Jitter measurement circuit for mixed signal production test

Measurement, 2007

This paper presents a novel low-cost jitter measurement circuit for production test. The hardware implementation is based on the so-called analytic signal method. The circuit consists of two parts: high-speed ADC sampling and DSP computation. The uniqueness of this circuit comes from the fact that the FPGA is used as both the ADC sampling controller and the main computation engine, which can significantly reduce the test cost. To validate the design effectiveness, measurements results have been compared between various instruments and this proposed circuit.

Measurement of timing jitter contributions in a dynamic test setup for A/D converters

IEEE Transactions on Instrumentation and Measurement, 2001

This article provides a new method which permits one to separate and to obtain an accurate estimation of timing jitter contributions appearing in an analog-to-digital (A/D) converter dynamic common test setup. The results are obtained using coherent sampling configuration and are independent of quantization and nonlinearities of the converter.

Built-in self-test approaches for analogue and mixed-signal integrated circuits

38th Midwest Symposium on Circuits and Systems. Proceedings, 1996

The increasing complexity of analogue mixed-signal integrated circuits is leading test engineers to propose self-test capabilities for these types of circuits. The use of on-chip structures for the test of analogue and mixedsignal parts allows for signi cant savings in expensive test equipment and reduces the chip cost. This eld has been the subject of substantial research over the last few years. This paper presents a survey of the most signi cant analogue and mixed-signal built-in self-test approaches.

Approximation Approach for Timing Jitter Characterization in Circuit Simulators

2003

A new computational concept of timing jitter is proposed that is suitable for exploitation in circuit simulators. It is based on the approximation of computed noise characteristics. To define jitter value the parameter representation is used. The desired parameters are obtained after noise simulation process in time domain by minimization of integral residual L 2 -norm. The approach is illustrated by examples of jitter computation using Spicelike simulator.

Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs

IEEE Transactions on Instrumentation and Measurement, 2005

We propose a novel on-chip circuit to measure the jitter present at the output of phase-locked loops (PLLs) used for generating phase-synchronous, frequency-multiplied clocks. This measure is performed at every period of the PLL reference clock, and a digital output encoded by means of a thermometer code is obtained. Such a digital output is then analyzed in order to confirm on-chip whether or not the jitter is within specifications. Our proposed circuit is able to test PLLs providing an output frequency in the gigahertz range. Compared to alternate techniques, that proposed here requires lower costs in terms of area overhead (requiring an area 12% of the PLLs' area) and circuit complexity, while featuring higher or comparable accuracy and lower or comparable test time. Index Terms-Jitter, on-chip measurement, phase-locked loops (PLLs), testing. I. INTRODUCTION P HASE-LOCKED loops (PLLs) are basic component blocks of today's ICs [1]. They are widely used for clock multiplication in microprocessor and data communication circuits [2]. The deviation in frequency and phase of the signal generated at the output of the PLL is known as PLL jitter. It may be due to power supply noise, PLL dead zone region, internal and external crosstalk, and potential noise associated with all ICs [3]. The continuous increase in the operation frequency of modern microprocessors and communication systems is tightening PLLs' jitter requirements to a few tens of picoseconds in order to prevent jitter from becoming a high percentage of the cycle time. Jitter out of specification may cause data loss or computational errors, with dramatic consequences on system reliability. These stringent requirements on PLLs' jitter have increased the relevance of jitter measurement techniques. Traditionally, jitter measurement has been performed off-chip by spectrum analyzers, automatic test equipment (ATE), real-time sampling oscilloscopes, or jitter-dedicated instruments, like time-interval analyzers (TIAs) and counter-timers. Clearly, jitter measurement relies on the utilized external equipment. This traditional approach has become extremely expensive for today's high-speed ICs. Consequently, several alternative off-chip methods, as well as on-chip solutions, have been proposed in literature (e.g., those in [4]-[12]).

Power Integrity Analysis For Jitter Characterization

2016

The years I spent at the National Institute of Technology have been full of unforgettable memories. Thanks to many people who deserve my highest gratitude. First of all, I am deeply grateful to my academic advisor, Prof. K. K. Mahapatra for the constant support at each step of the process. I would also like to express my appreciation to the Department of Electronics and Communication Engineering, specifically the team of VLSI and Embedded Systems for providing such a friendly and encouraging environment with all the required tools to support high quality academic research. I express my genuine appreciation to Prof. A. K. Swain, Prof. D. P. Acharya and Prof. Nurul Islam, who had presented the universe of VLSI and Embedded System and helped me learning different areas of my specialization. I am very grateful to Mr. Pratik Damle of S. T. Microelectronics for his mentorship and significant contribution to my academic research. I express my soulful gratitude to him for their invaluable guidance for my training and completion of thesis. I am truly appreciative to all my colleagues and different companions who had made my stay at NIT Rourkela and S.T. Microelectronics a charming experience. Last, but not the least, I express my deepest appreciation to my parents, Mr. N. T. Thomas and Mrs. Lilly Thomas and sister Lincy Thomas to whom I owe not only my success but every step of my life. I thank them for the consistent backing and support.

Testing analog and mixed-signal integrated circuits using oscillation-test method

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

A new low-cost test method for analog integrated circuits, called the oscillation test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which deviate the oscillation frequency from its tolerance band can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated, and the test time is very small because only a single output frequency is evaluated for each CUT. The oscillation frequency may be considered as a digital signal and therefore can be evaluated using pure digital circuitry. These characteristics imply that the oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this note, the validity of the proposed test method has been verified throughout various examples such as operational amplifiers, amplifiers, filters, and analog-todigital converters (ADC's). The simulations and practical implementation results affirm that the presented method assures a high fault coverage.

Mixed-signal on-chip timing measurements

Integration, the VLSI Journal, 1998

On-chip test techniques to reduce the dependence on external testers and to improve high-frequency measurement accuracy have become a major focus in test research and development. This paper reviews the fundamental theory of timing measurements, a popular requirement for on-chip tests, and describes a wide range of circuit techniques to implement the theory. Results are presented to verify the circuit performance and limitations. A framework for timing measurement is proposed to benchmark further developments in this area.

Integrated Design and Test of Mixed-Signal Circuits

Journal of Electronic Testing, 1999

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.