POETS: A Parallel Cluster Architecture for Spiking Neural Network (original) (raw)
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Challenges for large-scale implementations of spiking neural networks on FPGAs
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The last 50 years has witnessed considerable research in the area of neural networks resulting in a range of architectures, learning algorithms and demonstrative applications. A more recent research trend has focused on the biological plausibility of such networks as a closer abstraction to real neurons may offer improved performance in an adaptable, real-time environment. This poses considerable challenges for engineers particularly in terms of the requirement to realise a low-cost embedded solution. Programmable hardware has been widely recognised as an ideal platform for the adaptable requirements of neural networks and there has been considerable research reported in the literature. This paper aims to review this body of research to identify the key lessons learned and, in particular, to identify the remaining challenges for large-scale implementations of spiking neural networks on FPGAs. r
2008
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biological neuron/synaptic models. Also their routing structures cannot accommodate the high levels of neuron inter-connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing large scale SNNs on reconfigurable FPGAs. The paper presents a novel Field Programmable Neural Network (FPNN) architecture incorporating low power analogue synapse and a network on chip architecture for SNN routing and configuration. Initial results are presented.
Fpga Based Reconfigurable Implementations of Spiking Neural Networks: A Mini Review
2022
Due to the increasing data capacity, low power consumption, and high-speed data processing expectations of systems in our daily lives today, the Von Neumann bottleneck has become a more important problem than in the past. For these reasons, conventional computer architectures can no longer fully meet today's requirements. Neuromorphic designs have been considered an alternative solution for all, as they can mimic the human brain in terms of processing large amounts of data quickly with low power consumption. Although the success of traditional Artificial Neural Network methods is satisfactory, biological systems are still much more advantageous in terms of power consumption. Neuromorphic hardware architectures based on Spiking Neural Network (SNN), which are the most biologically plausible and are referred to as third-generation neural networks, overcome the Von Neumann bottleneck and provide a more suitable hardware structure for intelligent systems. The use of reconfigurable hardware for the implementation of neuromorphic architectures creates a faster and more updatable research field than integrated circuits and computational approaches. Therefore, this study has reviewed FPGA-based reconfigurable implementations of Spiking Neural Networks (SNN) in the literature and compared these studies in terms of power consumption, learning capability, resource consumption, and accuracy.
SNAVA-A real-time multi-FPGA multi-model spiking neural network simulation architecture
Neural networks : the official journal of the International Neural Network Society, 2018
Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to proto...
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Neuromorphic neural networks are of interest both from a biological point of view and in terms of robust signaling in noisy environments. The basic question however, is what type of architecture can be used to efficiently build such neural networks in hardware devices, in order to use them in real time process control problems. In this paper a novel, hardware implementation friendly, "pulse reactive" model of spiking neurons is described. This is used then to implement a fully connected network, yielding a high degree of parallelism. The modular neuron structure, acquired signals and a process control application are given.
An FPGA platform for on-line topology exploration of spiking neural networks
Microprocessors and Microsystems, 2005
In this paper we present a platform for evolving spiking neural networks on FPGAs. Embedded intelligent applications require both high performance, so as to exhibit real-time behavior, and flexibility, to cope with the adaptivity requirements. While hardware solutions offer performance, and software solutions offer flexibility, reconfigurable computing arises between these two types of solutions providing a trade-off between flexibility and performance. Our platform is described as a combination of three parts: a hardware substrate, a computing engine, and an adaptation mechanism. We present, also, results about the performance and synthesis of the neural network implementation on an FPGA.
An Efficient Implementation of a Realistic Spiking Neuron Model on an FPGA
2010
Hardware implementations of spiking neuron models have been studied over the years mainly in researches focused on bio-inspired systems and computational neuroscience. This introduced considerable challenges for researchers particularly in terms of the requirements to realise a efficient embedded solution which may provide artificial devices adaptability and performance in real-time environment. Thus, programmable hardware was widely used as a model for the adaptable requirements of neural networks. From this perspective, this paper describes an efficient implementation of a realistic spiking neuron model on a Field Programmable Gate Array (FPGA). A network consisting of 10 Izhikevich's neurons was produced, in a low-cost and low-density FPGA. It operates 100 times faster than in real time, and the perspectives of these results in newer models of FPGAs are promising.
On-line Topology Exploration of Spiking Neural Networks on FPGAs
In this paper we present a system for evolving spiking neural networks on FPGAs. Embedded intelligent applications require both high performance, so as to exhibit real-time behavior, and flexibility, to cope with the adaptivity requirements. While hardware solutions offer performance, and software solutions offer flexibility, reconfigurable computing arises between these two types of solutions providing a tradeoff between flexibility and performance. The system is described as a combination of 3 parts: a hardware platform, a computing engine, and an adaptation mechanism. Results about the performance and synthesis of the neural network implementation on an FPGA are presented.
Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs
Lecture Notes in Computer Science, 2005
The current growth of neuron technology is reflected by the increasing focus on this research area within the European research community. One topic is the implementation of neural networks (NNs) onto silicon. FPGAs provide an excellent platform for such implementations. The development of NNs has led to multiple abstractions for various generations. The different demands that each generation pose, present different design challenges. This has left ambiguous decisions for the neuroengineer into what model to implement. The authors have undertaken an investigation into four commonly selected neuron models, two classical models and two formal spike models. A software classification problem is combined with hardware resource requirements for FPGAs, implemented utilising a novel design flow. This provides an overall comparative analysis to be made and identification of the most suitable model to implement on an FPGA.