Design of High Speed All Digital Phase Lock Loop for FM Application (original) (raw)

All Digital Phase Lock Loop (ADPLL) is contributing in advancement in digital communication and control system since 1980. In this paper “High speed ADPLL for FM application” is proposed. The ADPLL is designed using phase detector, digital loop filter and increment-decrement counter. Here the speed of ADPLL is increased by using novel multiplexer based increment– decrement counter. The ADPLL using these blocks are simulated by using Xilinx 14.5. It is observed that the delay of proposed ADPLL is less compare to existing ADPLL [1]. Further, the proposed ADPLL is used to generate FM modulation by using interpolator method.