Design of High Speed All Digital Phase Lock Loop for FM Application (original) (raw)
Related papers
DESIGN IMPLEMENTATION OF DIGITAL FM MODULATOR & DEMODULATOR FOR SDR USING FPGA
This paper represents the recent advancement in the chip technology is integrating several sequential elements in System on Chip (SoC). But most of the circuits are using traditional clock distribution networks and facing the problem of skew and jitter problems. The clock signal generated by the oscillators and the flip-flops and registers are not receiving the clock pulse at the accurate time. The problem can be solved using Network of Phase-Locked Loop (PLL) oscillators coupled in phase. A phase locked loop ensures that the clock frequencies seen at the clock inputs of various registers and flip-flops match the frequency generated by the oscillator. The popular technique to demodulate FM signal is Phase Locked Loop (PLL). The existing technologies are based on software defined radio (SDR) [7, 8] and the demand needs programmable SDR instead of analog SDR. In SDR, Programmable digital devices are used and they transmit and receive the baseband signal at radio frequency. The recent cellular devices follow the communication protocol and provide connectivity to end user anywhere in the particular region.The design approach is based on digital components rather than analog components such as phase detector, loop filter and Voltage Controlled Oscillator (VCO). The signal is presented using digital words instead of analog voltages. In digital FM receiver, PLL is the main part to capture and lock the signals at different frequency and phase. The main purpose of PLL is to maintain the coherence between the modulated signal frequency (fi) and the respective frequency (fo), with the concept of phase comparison. PLL permits to track the frequency changes of applied input signals, as it is locked once. The paper focuses on the design, FPGA implementation of FM receiver integrated with digital PLL. There is a use of 8 bit analog to digital conversion (ADC) circuit, which is accepting frequency modulated signal as a series of digital numerical values. The same signals are demodulated by the receiver on every clock cycle. The paper proposed the design and FPGA implementation of digital PLL and programmable all FM receiver. The design is developed in Xilinx 14.2 ISE software and simulated in Modelsim 10.1b software with the help of VHDL programming language and the targeted onVirtex-5 FPGA.
2009 Seventh Annual Communication Networks and Services Research Conference, 2009
In this paper a novel user-friendly implementation of an all-digital phase-locked loop (ADPLL) is presented. Its novelty lies in the fact that the very basic functions of the ADPLL are kept in the top module Verilog file. Against the normal design practice, all of the main math functions were implemented using the sub-modules placed outside but called from within the top module. This way ADPLL can be easily implemented in a low cost FPGA. Further, the implementation details of an ADPLL, which are not reported previously in a single shot, are described altogether for the first time. The reconfigurable ADPLL is then implemented in a transceiver architecture and tested with real signals received wirelessly. The recovered IQ constellation EVM of 9.0336% was obtained, which is quite practical. This proves the feasibility of the ADPLL not only in simulations but in a real communication system. The ADPLL designed this way can be used in any communication system, although preferably for high data rate transceiver applications.
A novel phase detection system for linear all-digital phase locked loop
2012 Students Conference on Engineering and Systems, 2012
In this paper, a novel fast phase detection system for all-digital phase locked loop (ADPLL) is presented. The phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase. 16-bit CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detector system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The phase detection system although providing a definite advantage over conventional analog phase detectors, The Hilbert filter implemented in this paper has been designed using a method based on complex, multiplier less sampling filters. A comparison has been drawn between the continuous PLL model's phase detection system and the proposed method for effectiveness of the study. The studied system is modeled and tested in the MATLAB/Simulink environment.
Designs of All Digital Phase Locked Loop
2014 Recent Advances in Engineering and Computational Sciences (RAECS), 2014
Phase Locked Loop (PLL) is a feedback system that is configured as frequency multipliers, tracking generators, demodulators and clock recovery circuits. Today the most challenging requirement engineers' face is design of fast locking PLL with low jitter. Many analog techniques are proposed to fulfill the demand but they result in increasing complexity of design and long lock in time. In this paper, review of advantages of an All-Digital phase locked loop (ADPLL) over an analog phase locked loop (APLL) in terms of stability, programmability is studied. Various approaches to design the blocks of ADPLL till now adopted are presented in this paper.
Digital phase-locked loop and its realization
The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the DPLL system is first formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realize this DPLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realized by the EKF. The proposed DPLL has a simple structure and low realization complexity. Computer simulations for a conventional DPLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realization can estimate the input phase rapidly without causing a large jittering.
Digital Implementation of Frequency and Phase Locked Loops
Real time estimation of frequency, phase and magnitude of a pure sinusoidal signal is a classical problem that has many practical applications. Phase looked loops are widely used in these applications, but using PLL in these applications is more costly. The novel approach of designing Adaptive Frequency and Phase Locked Loop (FPLL) for these applications is proposed and discussed. This paper presents the digital implementation of Adaptive Frequency and Phase Locked Loop (FPLL) and also aims at in detail deliberation of simulation. The logics of adaptive FPLL is realized in digital domain using VHDL and the inevitable complications of algebraic loop in closed loop algorithm are addressed. Also given suggestion for selecting the number system for the practical DSP applications and discussed the implementation issues of closed loop algorithms in the z-domain compared with the s-domain.
FPGA Based Digital Phase Locked Loop using VHDL Coding
PLL is contributing vital role in advancement in electronic and digital communication since 1932. In analog television receivers since at least at late 1930s, phase locked loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal. PLL may be implemented either in analog circuit or in digital circuits. Analog and digital PLL circuits consists of four basic element i.e phase detector, low pass filter , variable frequency oscillator and feedback path. There are several variation of PLL, DPLL is one of the variation. This paper gives basic details and design of DPLL by using edge trigger JK as phase detector and NCO in VHDL using Xillinx.
A Comparative Analysis on All Digital Phase Locked-Loops
In this paper we have designed and implemented two all-digital phase-locked loop models one with an XOR gate as phase detector and the other with edge triggered JK flip flop as Phase Detector. The proposed models are implemented by using Very High Speed Integrated Circuit Hardware Description Language. The simulation has been performed in ISE Xilinx 14.2 software platform to study the power consumptions and synthesis characteristics of the models. The power consumptions of the models are evaluated from Xilinx Power Estimator. It is observed that the power consumption of the model with XOR gate and with edge triggered JK FF phase detector are recorded to be 15 mW and 21 mW respectively at ambient temperature of 25° C.
All digital phase-locked loop: concepts, design and applications
IEE Proceedings F Radar and Signal Processing, 1989
The concepts of an all digital phaselocked loop (DPLL), which contains a purely digital phase detector, loop filter and voltagecontrolled oscillator, are explained. A second order DPLL is considered and analysed using the Z-transform technique. Implementation of the DPLL, based on the CMOS digital signal processor TMS 320C25, and the experimental results, are presented. Potential applications are also discussed.
IJERT-Design of an Efficient Phase Frequency Detector for a Digital Phase Locked Loop
International Journal of Engineering Research and Technology (IJERT), 2016
https://www.ijert.org/design-of-an-efficient-phase-frequency-detector-for-a-digital-phase-locked-loop https://www.ijert.org/research/design-of-an-efficient-phase-frequency-detector-for-a-digital-phase-locked-loop-IJERTV5IS040128.pdf This paper outlines the design and analysis of the digital phase locked loop (DPLL). It also demonstrates the feasibility of the DPLL in the various applications. The proposed phase frequency detector (PFD) uses 26 transistors analogous to the conventional PFD which uses 54 transistors. It has been observed that the lock in time of the DPLL is very less. In addition to these, an overview on the designing of the charge pump and loop filter is also discussed. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK180 library of 180 nm technology with a supply voltage of 1.8 V.