A novel method for designing odd base quantum half adder (original) (raw)
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A novel method for the synthesis of odd base quantum full adder
2010
For various reasons in recent years the interest in building quantum computers has increased gradually. To do the calculations in quantum computer we need quantum arithmetic logic unit (ALU). The building block of quantum ALU is quantum adder. In quantum computer multivalued logic is possible. In this paper a generalized circuit has been proposed to build odd base multivalued quantum full adder. A novel approach has been taken to minimize the total no. of gates. Muthukrishnan-Stroud gates and quantum shift gates have been combined to achieve the minimal circuit.
Design of a Ternary Reversible/Quantum Adder using Genetic Algorithm
International Journal of Information Technology and Computer Science, 2015
Typical methods of quantum/reversible synthesis are based on using the binary character of quantum computing. However, multi-valued logic is a promising choice for future computer technologies, given a set of advantages when comparing to binary circuits. In this work, we have developed a genetic algorithm-based synthesis of ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding that we present, as well as a judicious choice of algorithm parameters, allowed obtaining circuits for half-adder and full adder which are better than other published methods in terms of cost, delay times and amount of input ancillary bits. A structure of the circuits is analyzed in details, based on their decomposition.
A Novel Design of Half and Full Adder using Basic QCA Gates
International Journal of Computer Applications, 2014
This paper presents the novel design of half adder and full adder using reduced number of QCA gates.This design utilizes the unique characteristics of QCA to design a half and a full adder.The basic component of QCA is a cell consisting of two electrons and four logically interacting quantum dots.Simulation indicates a fast,efficient and very attractive performance(i.e.complexity,area and delay)
Design and Implementation of Quantum half Adder and Full adder Using IBM Quantum Experience
International Journal of Advanced Trends in Computer Science and Engineering, 2021
Quantum machine learning is the combination of quantum computing and classical machine learning. It helps in solving the problems of one field to another field. Quantum computational power can be advantageous in handling huge data at a faster rate.In this regard, quantum computational power can be advantageous in handling such huge data at a faster rate. Classical machine learning is about trying to find patterns in data and using those patterns to predict future events. Quantum systems, on the other hand, produces typical patterns which are not producible by classical systems, thereby postulating that quantum computers may overtake classical computers on machine learning tasks. Hence the whole motivation in this work is on understanding and analysing the half adder and full adder circuit design using Quantum mechanics.
Low Quantum Cost Construction for Adder and Symmetric Boolean Function
2017
Reversible logic design has been one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. Quantum computing necessitates the design of circuits via reversible logic gates. Efficient reversible circuit can be constructed by achieving low ancilla count, reducing logical depth and lowering Quantum costs. Generalized Peres gates have recently been realized with very low Quantum Cost (QC) by utilizing Quantum rotation gates. This is utilized in recent literature for efficient reversible circuit constructions for symmetric Boolean functions. In this paper, we extend this line of construction further by demonstrating efficient realization of adder circuits. In particular, we revisit the adder construction of Vedral, Barenco and Eckert to show that improvement of gate count and QC is achievable by exploiting a construction based only on Peres gates. We also report improved constructions of symmetric Boolean functions by following ...
A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder
Periodica Polytechnica Electrical Engineering and Computer Science
The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed...
New Design of Reversible Full Adder/Subtractor Using R Gate
International Journal of Theoretical Physics
Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R 3 gate to perform the quantum half adder/ subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as AN D, XOR, N AN D, XN OR, N OT and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, 1 the quantum cost and the delay. The proposed designs are implemented and tested using GAP software.
International Journal of Modern Education and Computer Science, 2015
This paper proposes a new 4×4 reversible logic gate which is named as MOG. Reversible gates are logical basic units, having equal number of input and output lines, which can reduce power dissipation in digital systems design through their reversibility feature; because there is a one-to-one corresponding between their input and outputs vectors. The most significant aspect of the MOG gate is that it is a universal gate and has the ability of calculating any logical function on its own. We have also proposed quantum representation of the MOG gate with optimal quantum cost equal to 11. Then, it has been proved that MOG gate can be used to produce a cost efficient reversible full adder/subtractor cell in terms of reversible and quantum metrics. The proposed reversible full adder/subtractor design using MOG gate is a completely optimized circuit in terms of the number of reversible gates, the number of constant inputs, and the number of garbage outputs because it can work with the minimum possible amounts of these reversible metrics. Additionally, it is more efficient than the existing counterparts in terms of quantum cost. The full adder/subtractor cell is an important circuit in VLSI and digital signal processing applications. A lot of works have been done toward designing reversible full adder/subtractors in the literature; but there is no an optimized design with quantum implementation. To prove the applicability of the proposed design in large processing scales, we have constructed 8-bits reversible ripple carry full adder/subtractor circuit using MOG gates. Results have shown the superiority of our proposed design compared with other 8-bits similar designs.
Quantum Realization of Ternary Adder Circuits
Ternary quantum circuits have recently been introduced to realize ternary logic functions. In this paper realizations of ternary half-and full-adder circuits using generalized ternary gates (GTG) are proposed, which are more efficient than the previously published realizations.
Quantum ternary parallel adder/subtractor with partially-look-ahead carry
Journal of Systems Architecture, 2007
Multiple-valued quantum circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum circuits. Binary parallel adder/subtractor is central to the ALU of a classical computer and its quantum counterpart is used in oracles – the most important part that is designed for quantum algorithms. Many NP-hard problems can be solved more efficiently