A Reconfigurable Architecture for Robotic Stereo Vi sion (original) (raw)

2012

A reconfigurable architecture for dense stereo is presented as an observation framework for a real-ti me implementation of the simultaneous localization and mapping problem in robotics. The reconfigurable sen sor detects point features as corners from stereo image pairs, in order to use them at the measurement update stag e of the procedure. The main hardware blocks are a dense depth stereo accelerator, a left and right image co rner detector and a stage performing left-right consiste ncy check for the detected features. For the stereo-pro cessor stage we have implemented and tested both a localmatching method based on the Sum of Absolute Differences (SAD) and a global-matching component based on a maximum-likelihood dynamic programming technique (MLDP). The system includes a Nios II processor for data control and a USB 2.0 interface for host communication. The proposed hardware is applied as the sensor part in a real-time robotic localization and mapping experiment with the help of...

An FPGA-CAPH stereo matching processor based on the Sum of Hamming Distances

2016

Stereo matching is a useful algorithm to infer depth information from two or more of images and has uses in mobile robotics, three-dimensional building mapping and three-dimensional reconstruction of objects. In area-based algorithms, the similarity between one pixel of an image (key frame) and one pixel of another image is measured using a correlation index computed on neighbors of these pixels (correlation windows). In order to preserve edges, the use of small correlation windows is necessary while for homogeneous areas, large windows are required. In addition, to improve the execution time, stereo matching algorithms often are implemented in dedicated hardware such as FPGA or GPU devices. In this article, we present an FPGA stereo matching processor based on the Sum of Hamming Distances (SHD). We propose a grayscale-based similarity criterion, which allows separating the objects and background from the correlation window. By using the similarity criterion, it is possible to improve the performance of any grayscale-based correlation coefficient and reach high performance for homogeneous areas and edges. The developed FPGA architecture reaches high performance compared to other real-time stereo matching algorithms, up to 10% more accuracy and enables to increase the processing speed near to 20 megapixels per second.

Hardware principles for the design of a stereo-matching state machine

This paper presents basic design principles for hardware implementation of a two-pass stereo-matching algorithm based on dynamic programming. For the first-pass a state-machine is proposed for the recursive calculation of the cost-function. The state-machine works along the diagonal of a 2-D disparity space for each epipolar pair of image scan-lines. On-chip local RAM stores tags that denote the minimum transition cost to every point in the disparity space among possible costs from all three neighboring points. All calculations are within a pre-determined useful disparity range. For the second pass, hardware rules are presented that produce the correct disparity per pixel, by backtracking stored cost values. Hard-ware stages are structured along a fully parallel pipeline, that outputs disparities in step with the input serial pixel stream at clock rate.

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