Advanced Cu Electroplating Process for Any Layer Via Fill Applications with Thin Surface Copper (original) (raw)
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2018
Revolutionary new consumer electronic products and their miniaturization drives capitalization on the latest technologies available to increase the functionality of PCBs. High density interconnect (HDI) technology is one of the fastest growing in printed circuit board industry. This technology allow us to utilize the PCB real estate more efficiently by including laser microvias, fine lines and high performance thin materials. The increased density enables more functions per unit area. Advanced HDI technology have multilayer PCBs with copper filled stacked microvias. These Advanced HDI PCBs could house more complex interconnect structures. These very complex structures provide the necessary connection pathways for modern day large pin-count chips. Microvias play crucial role in HDI designs, mechanical or laser drilling of blind micro vias (BMV’s) and successive filling has become the standard manufacturing technique. Specially, small microvias laser drilling is the only possible way ...
High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking
Journal of The Electrochemical Society, 2005
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 m deep and 10 m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu͑I͒ thiolate accelerant.
High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking
Journal of The Electrochemical Society, 2003
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 m deep and 10 m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu͑I͒ thiolate accelerant.
Copper plating for 3D interconnects
Microelectronic Engineering, 2011
In this paper we report on Cu plating of through-silicon-vias (TSV-s) using in-house made acidic Cu bath with model additives (SPS, PEG, and JGB). Although the model additives might not be as potent as commercial additives, they have been studied in detail, and their role in Cu plating has been described extensively in scientific literature. This in turn allows deeper insight into how changes in bath composition affect the plating mechanism and Cu via-fill.
2007
This paper presents a novel technology for copper electroplating in high aspect ratio silicon vias. The described approach is based on the bottom-up technology with the use of a new specifically designed electroplating holder for local sealing and filling of the vias. The technological steps are described and demonstrated for 20µm wide vias with an aspect ratio of 15. Moreover, a simplified simulation model is presented in order to explain the local sealing phenomenon and the subsequent electroplating.
2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2018
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. There are 4 main drivers which forced the chemical supply industry to introduce new electrolytic copper processes with the new feature of "filling" capability over the years. The 1st driver is the continuous miniaturization of electronics. The first blind microvias were introduced with HDI technology in the late 1980s and early 1990s. In 1996, the IC Substrate market started to fill the micro vias. "Plugging" technologies were introduced in order to stack the micro vias to save space or to create "via in Pad" structures. This "plugging" technology with conductive paste was very expensive because of the additional process steps required. Today copper filled microvias are the standard for almost all HDI PCB manufacturers. The 2nd driver is the thermal management on a substrate. Solutions were needed to integrate features with high thermal conductivity to manage the heat transfer on the substrates from one side to the other in order to minimize hot spots on the electronic devices over a lifetime. The higher the chip performance is, the more it tends to generate local heat-spots resulting in an early loss of the electronics in the field. The reason for this is the degeneration of various materials at these local hot spots. Meanwhile the complete copper filled through holes was realized in 2006, by bridge plating or X-plating technology. Nowadays, completely copper filled through hole structures are at the leading edge of technology for thermal via structures because copper has almost the best thermal conductivity and it has to be plated nonetheless. The 3rd driver is the signal frequency. Electronic signals in an electronic package or inside of a PCB are increasing over time and continue to do so. Stacked microvias and fan-out vias are becoming more and more of a disadvantage for the transmission of high frequency signals, due to the fact of creating resistances at high frequencies. Therefore the push of high frequency applications further increased the demand for technologies like copper filled through holes. The 4th driver especially for through hole filling, is the quality-yield aspect. The alternatives for electroplated copper filled through holes, requires many additional process steps, or new materials such as plugging pastes. Each of these additional process steps or materials introduces a variety of risks and manufacturing problems resulting in lower yield. Therefore the "one step" solution to fill through holes with copper is the preferred solution, without introducing new materials into the PCB. This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs. The paper will contain aspect ratios, dimensions and results of plated through holes used today in high volume manufacturing for microvia and through hole filling with electroplated copper. Furthermore, it will also show feasibility studies of new electroplated structures for future applications such as copper pillar plating on IC-substrates.
Vapor Deposition of Highly Conformal Copper Seed Layers for Plating Through-Silicon Vias (TSVs)
Journal of The Electrochemical Society, 2012
Through-silicon vias (TSV) will speed up interconnections between chips. Manufacturable and cost-effective TSVs will allow faster computer systems. In this paper, we report the successful formation of seed layers for plating copper TSVs with aspect ratios greater than 25:1. Following the rapid atomic layer deposition (ALD) of a conformal insulating layer of silica inside the silicon vias, manganese nitride (Mn 4 N) is deposited conformally on the silica surface by chemical vapor deposition (CVD). Mn 4 N forms an effective copper diffusion barrier and provides strong adhesion between the silica and the subsequently-deposited copper. Conformal copper or copper-manganese alloy films are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process. Diffusion of manganese during post-deposition annealing further enhances the barrier and adhesion properties at the copper/dielectric interface.
Gap filling with PVD processes for copper metallized integrated circuits
Microelectronic Engineering, 1997
The paper presents the results of two PVD techniques used for trench and via filling in copper-based metallization systems. The structure size is scaled down to 0.5 p,m and the aspect ratio (ratio of depth to width) is coming up to about 2.5. The patterning of the copper lines is performed by CMP (damascene technique). The first dc magnetron sputtering is optimized for trench filling with aspect ratios up to 1 by using variation of the distance between the substrate and the sputter target. It is shown that this variation is more effective for getting better filling results in comparison with variation of the deposition parameters like dc power, substrate temperature and substrate rf bias. Besides alternative investigated filling techniques like copper reflow, copper self-sputtering or ICP/ECR-based ionised sputtering the second high current pulsed arc deposition is performed to reach void-free filled vias and trenches with aspect ratios of 2. The typical problem with droplets is minimized. The first results show that the performance of this PVD technique is comparable with those of the above-mentioned filling methods and with copper CVD too. Additionally, it seems possible to use the deposition process in such a way that a Ta diffusion barrier can be deposited either conformally or without a noticeable layer growth on the top of the structure.
Filling a Narrow and High Aspect-Ratio Trench with Electro-Cu Plating
MATERIALS TRANSACTIONS, 2006
Copper electroplating has been used for making interconnections in large-scale integration (LSI). Sub-100-nm-wide, deep trenches with aspect-ratios over 6 were fully filled by optimizing DC and pulse electroplating processes. Grain sizes of Cu of sub-100-nm wide trenches after electroplating were 70 nm for DC electroplating and 58 nm for pulse electroplating. The Cu grain sizes of Cu interconnects by DC plating after electroplating increased with the annealing temperature.
ECS Transactions, 2014
Among all the Ru-based substrates, mixed-phase RuTa liners grown by physical vapor deposition have been explored as potential directly-platable diffusion barrier candidates. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of the applied waveform, electrical contacts and suppressor chemistry have been investigated. In order to enhance copper nucleation and wafer scale edge-to-center copper front propagation rate, a liner surface cleaning protocol is developed. The copper front propagation across the 300 mm wafer is reported as a function of the RuTa film thickness. An optimized copper direct plating process on RuTa layers as thin as 4 nm is integrated in 90 and 30 nm half pitch single and dual damascene structures. Results in terms of compatibility of the direct plated copper with the following chemical mechanical planarization step complemented with physical and electrical characterization data are reported. The direct filling of ∼25 nm sacrificial fin structures is also investigated.