Full Adder/Subtractor Circuit Using Reversible Logic Gates (original) (raw)
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IJERT-Design and Analysis of Low Power Reversible Adder/Subtractor Circuits
International Journal of Engineering Research and Technology (IJERT), 2020
https://www.ijert.org/design-and-analysis-of-low-power-reversible-adder-subtractor-circuits https://www.ijert.org/research/design-and-analysis-of-low-power-reversible-adder-subtractor-circuits-IJERTV9IS090366.pdf In recent years, reversible logic has become a promising technology in the areas of low power VLSI design, nanotechnology, quantum computing and optical computing. The performance and reliability of digital systems which are now implemented using conventional logic gates can be enhanced by the usage of reversible logic gates, which pave for low power consumption and lesser quantum delays, thus increasing the speed of computation. Adder/subtractor circuits form the fundamental block in the arithmetic and logic unit of processors and other digital logic programmable devices. The performance of a digital system, its speed and throughput depend critically on the way these circuits are designed. Adder circuits are used in the Graphics Processing Unit(GPU) of computers for graphics applications to reduce complexity. Any way to enhance the performance and computational speed of these circuits will pave way for a better ALU. Incorporating the concepts of reversible computing in the design of adder/subtractor circuits can significantly enhance the performance and speed of operation of digital systems. In this paper, two existing adder/subtractor designs and a novel design are compared, analyzed for different bit lengths (1,8,16,32,64). Detailed analysis of reversible logic design parameters, power consumption parameters, and FPGA utilization parameters is carried out. These designs are analyzed and simulated using the Xilinx Vivado tool and implemented on Zedboard Zynq 7000 Evaluation and Development kit(xc7z020clg484-1). The proposed design outperforms the existing designs.
Cost Efficient Design of Reversible Adder Circuits for Low Power Applications
A large amount of research is currently going on in the field of reversible logic, which have low heat dissipation, low power consumption, which is the main factor to apply reversible in digital VLSI circuit design.This paper introduces reversible gate named as ‘Inventive0 gate’. The novel gate is synthesis the efficient adder modules with minimum garbage output and gate count. The Inventive0 gate capable of implementing a 4-bit ripple carry adder and carry skip adders. It is presented that Inventive0 gate is much more efficient and optimized approach as compared to their existing design, in terms of gate count, garbage outputs and constant inputs. In addition, some popular available reversible gates are implemented in the MOS transistor design the implementation kept in mind for minimum MOS transistor count and are completely reversible in behaviour more precise forward and backward computation. Lesser architectural complexity show that the novel designs are compact, fast as well as low power.
A LOW POWER ADDER USING REVERSIBLE LOGIC GATES
IJRET, 2012
Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition, subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates
HAS: HIGH SPEED & POWER EFFICIENT HYBRID ADDER/SUBTRACTOR DESIGN USING REVERSIBLE LOGIC
IRJET, 2022
Reversible logic is extensively contemplating as the potential logic design style for execution in modern technologies. Such as, nanotechnology and QC. In this paper, we have designed hybrid full adder and full subtractor using Feynman gate and TR gate. Feynman gate and TR gate is designed using pas transistor logic. The simulation results show the high speed, decrease in size and lower power dissipation can be realized with the HAS: Hybrid Adder/Subtractor design using reversible logic. The schematics are analyzed in DSCH 2 and Layouts are designed in MICROWIND 2. we improved the speed 1ps, power 6.23mW, and area 74.504mm2.
International Journal of Circuit Theory and Applications, 2020
Nanotechnology and very large-scale integration (VLSI) fabrication have a reflective productivity. The growth of one demands the growth of the other. In nanotechnology, quantum-dot cellular automata (QCA) secures as the best alternative for replacement of complementary metal-oxide semiconductor (CMOS) technology for integrated circuit (IC) fabrication. This paper presents an integration of the two domains wherein a novel ultraefficient, multioperative 3 × 3 universal reversible gate, Sadat Farah Vijay (SFV)-QCA, is proposed and implemented in QCA technology using majority voter approach. SFV-QCA gate is redesigned and restructured using precise QCA cell interaction for optimization. The basic logic gates are implemented using the proposed SFV-QCA gate to validate its universality. All the 13 standard Boolean functions are implemented using SFV-QCA to demonstrate its multioperation nature. One-bit full adder and subtractor circuits are designed using SFV-QCA gate and compared with the previous works. The analysis of the SFV-QCA gate shows that it is ultraefficient and more robust as compared to previous works. Energy dissipation analysis of the designs has also been presented, and the investigation establishes minimum energy dissipation of the designs that confirms ultrahigh efficient designs.
Design of a novel reversible multiplier circuit using modified full adder
2010 International Conference On Computer Design and Applications, 2010
Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. It is also better than the existing counterparts in term of number of gates, garbage outputs and constant inputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "HNG". The reversible HNG gate can work singly as a reversible full adder. In this paper we use HNG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication. We can use it to construct more complex systems in nanotechnology.
A New Reversible Design of Adder & Subtractor Using Reversible Logic Gates
2018
Modern VLSI design circuitry is used for low power consumption which is the requirements of ICs. Reversible logic has its tremendous applications and importance because it doesn’t lose any single bit of information of no information while performing computation bit loss during computation; it reflects the result in low power dissipation. However, we have to convert the reversible circuits into fault tolerant reversible circuits; it helps to detect the occurrence of errors and faults. Parity preserving property can be used for this. A new parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work as a full adder as well as full subtractor by using one P2RG and Fredkin gate only. This proposed design is very good in terms of gate count, garbage outputs, constant inputs and area than the existing similitude. The concept behind the reversible logic circuits is that the inputs and outputs are same.
Reversible logic gate implementation as switch controlled reversible full adder/subtractor
2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014), 2014
Reversible computation plays an important role in low power circuit design and efficient energy recycling. In this paper, a switch controlled efficient Reversible Full Adder/Subtractor (RFAS) is presented. RFAS block is further used in the construction of n-bit adder/subtractor. The proposed design is analyzed and compared against the existing reversible techniques. Features such as, hardware cost, logic calculation and gate count etc. are investigated to show the efficiency of the design. Simulation results are verified using Altera Quartus II and ModelSim software. Observations suggest that the circuit offers lesser hardware complexity compared to the existing reversible full adder.
Full Adder using Reversible Logic
International Journal for Research in Applied Science and Engineering Technology IJRASET, 2020
Reversible logic gates are very popular among upcoming future computing technologies. In the field of quantum computing ,low power VLSI devise, nanotechnology, DNA computing optical computing , quantum-dot cellular automata reversible logic circuits have various applications which are helping the world to do their work more easily [3]. Despite them, Quantum computers are the another major application of reversible logic ,these are certain areas in which the quantum devices are essential, with less power dissipation and at ultra high speed these devices can be ideally operated, these devices must build from reversible logic components, such requirements and versatility of reversible logic makes the reversible logic as one of the most versatile area for the researchers to discover new devises based on it and bring a revolutionary change in the field of computing technologies and various other fields in which reversible logic is a better option to be used in the past few decades .In past few decades reversible logic has became the major source of designing the modern circuits which can be helpful in various devices. Along with space and power, the delay is one of the significant issues in VLSI design. Reversible logic is becoming a huge source of research day by day, having the area for research in the designing of the complementary metal oxide semiconductor field effect transistor with the small amount of power consumption. The design proposed in the paper of full Adder circuit is one of the example of such circuit which is implemented by using reversible logic gates and hence the design proposed in this paper operated as reversible full adder. With much lesser complexity in the terms of hardware and lesser efficiency in terms of undesired outputs , gate count and same input the proposed design is most reliable than the presented ones. The reversible logic gates provided us a drastic change in the operation of electronic devices by using of fast switching operation of the gate used in the designing of reversible logic structure. Finally we can say that from the above illustration the reliability of the proposed design is increased. Keyword: Reversible, Fredkin gate, full adder, delay. I. INTRODUCTION In the present era the reversible logic design is gaining more attention due to its zero energy dissipation as no energy is being lost and low power consumption as the power consumed by it is less. Under the ideal condition the power dissipation of reversible logic is zero [1]. The relation between input and output reversible circuits have a monotonic mapping , thus, the vector of the input stage can always reconstruct from the output stage vectors. Rolf Landauer, in 1961, stated that whenever we use a logically irreversible gate, we dissipate energy in the surrounding INFORMATION LOSS=ENERGY LOSS That is the loss of one bit of information dissipate KTln2 of energy in irreversible gate due to which the heat energy dissipated, which degrade the output and result in the drop of the duration of the component. therefore due to this loss of information certain adverse effect on components may occur. Whereas in the reversible gate, no information is lost, hence there is no adverse effect on components, which leads to improvement in energy efficiency improvements and performance. which results into a improved version of circuits. The scientist Bennett has shown in 1970's that if the network permit the regeneration of the input by help of output then energy will not liberated from the system will not equal to KTln2[1]. The reversible logic consist of both frontend and backend. In Reversible logic the system follows the process of running both forward and backward. Therefore by computing backward we easily recover the earlier stage. Reversible logic is the most convenient and efficient way of designing the circuits. Some important logic gates in reversible logic gate Feynman gate, double Feynman gate, Friedkin gate, Toffoli gate, Peres gate, etc. Reversible compute have certain uses in the field of computer security and low power CMOS, quantum Computer nanotechnology and many more [4]. It has a vast field of application. Reversible logic can be applied in the implementation of various technologies it is helpful in designing different kinds of circuit for different applications. These logic gates having the capability to store the information in them without any loss of data during the system processing. These gates also maintain the system integrity and makes the data confidential.
Design of High-speed low power Reversible Logic BCD Adder Using HNG gate
2009
Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD) adder in reversible logic. The design reduces the number of gate operations compared to the existing BCD adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay. We can use it to construct more complex systems in