A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC (original) (raw)
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IEEE Electron Device Letters, 2000
In the family of wide band gap materials (silicon carbide, the group III nitrides and diamond), SiC is the only semiconductor that has a native oxide, and metal-oxide-semiconductor field effect transistors (MOSFETs) have been fabricated using both 4H-and 6H-SiC. The 4H polytype has higher bulk carrier mobility [1], and is hence the polytype of choice for power MOSFET fabrication. However, reported channel mobilities for 4H n-channel, inversion mode devices are substantially lower than for 6H-MOSFETs. For power device applications, the advantage provided by 4H-SiC of lower epilayer resistance for a given operating voltage is compromised by the low channel mobility. Schorner, et al. [2] attribute the poorer performance of 4H devices to a large, broad interface state density located at approximately 2.9eV above the valence band edge in both polytypes. More of these states lie in the band gap for 4H-SiC (Egap ~ 3.3eV) compared to 6H-SiC (Egap ~ 3eV) where they act to reduce channel mobility through field termination, carrier trapping and Coulomb scattering. Afanasev, et al. proposed that interface states in SiC/SiO2 structures result from carbon clusters at the interface and defects in a nearinterface sub-oxide that is produced when the oxidation process is terminated. The large interface trap density near the conduction band edge proposed by Schorner, et al. has been observed experimentally for both n-SiC and p-SiC . Li, et al. [7] originally reported improvements in the electrical performance of dry oxides on 6H-SiC annealed in nitric oxide (NO). We have grown oxides on 4H-SiC using standard thermal techniques [8] and conducted post oxidation anneals in . We find that the interface state density near the conduction band edge in n-4H-SiC can be reduced to levels comparable to the interface state density near the conduction band edge in 6H-SiC. Furthermore, the effective channel mobility for inversionmode 4H-SiC MOSFETs improves significantly following high temperature anneals in nitric oxide.
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Solid-State Electronics, 2005
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DC characterization of 4H-SiC depletion mode MOS field effect transistor
Solid-State Electronics, 2006
A depletion mode metal-oxide-semiconductor field effect transistor (MOSFET) has been fabricated using 4H-SiC. The basic structure is the same as that of a conventional metal-semiconductor FET (MESFET), except that the Schottky barrier gate is replaced by a MOS gate that comprises a 50 nm silicon oxide (SiO 2 ). The device has a pinch-off voltage of À1.0 V and a flat band voltage of 4.0 V. The drain current of the device can be substantially increased compared to the case of MESFET when a large positive gate voltage is applied, resulting in strong accumulation of electrons in the n-channel. Specifically, at a drain voltage of 25 V, the drain current is found to increase by 3.3 times when V GS is increased from 4.0 V (flat band condition) to 11.0 V (strong accumulation). Such gate bias condition, which is not possible in MESFETs, renders such devices ideal for high power applications. The electron mobility in the accumulation layer was found to be about 17.5 cm 2 /V s.
A New Spice Macromodel of 4H-SiC Vertical Double Implanted MOSFET (DIMOS)
Microelectronics and Solid State Electronics, 2012
The4H-SiCvert ical double Imp lanted MOSFET (DIM OS) offers advantages over conventional silicon devices, enabling high system efficiency and/or reduced system size, weight and cost through its higher frequency operation. Co mpared to the best silicon IGBTs, the SiC device will improve system efficiency up to 2% and operate at 2-5 times the switching frequencies.In this paper we present an equivalent circuit Spice of 4H-SiC DIM OSFET fo r a wide temperature range. Simu lation for DC characteristics (I-V) of the SiC M OSFET with the exact device geometry is carried out using the commercial device simu lator Spice. All Sp ice parameters are extracted fro m the measurements, and a SPICE model for the DIMOS transistor has been developed and implemented in the circuit simu lator Orcad PSpice 10.5. The temperature dependent behaviour was simulated and analysed. A good agreement between the Spice simulat ion and analytical model evaluation for SiC DIMOS is demonstrated. Model parameters can be adjusted to obtain an optimu m device to be used in power system applications.