200-nm InGaAs/InP type I DHBT employing a dual-sidewall emitter process demonstrating fmax> 800 GHz and fτ= 360 GHz (original) (raw)
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Ultra high-speed InP/InGaAs DHBTs with f t of 203 GHz
Journal of Semiconductors, 2009
InP/InGaAs/InP double heterojunction bipolar transistors (DHBTs) were designed for wide band digital and analog circuits, and fabricated using a conventional mesa structure with benzocyclobutene (BCB) passivation and planarization process techniques. Our devices exhibit a maximum f t of 203 GHz, which is the highest f t for DHBTs in mainland China. The emitter size is 1.0 × 20 µm 2. The DC current gain β is 166, and BV CEO = 4.34 V. The devices reported here employ a 40 nm highly doped InGaAs base region and a 203 nm InGaAsP composite structure. They are suitable for high speed and intermediate power applications.
InGaAs-InP Mesa DHBTs With Simultaneously High and and Low Ratio
2000
We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz and 459-GHz max , which is to our knowledge the highest reported for a mesa InP DHBT-as well as the highest simultaneous and max for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a cb ratio of 0.28 ps/V at cb = 0 5 V. The BR CEO is
InGaAs–InP Mesa DHBTs With Simultaneously High$f_tau$and$f_max$and Low$C_rm cb/I_c$Ratio
IEEE Electron Device Letters, 2004
We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz and 459-GHz max , which is to our knowledge the highest reported for a mesa InP DHBT-as well as the highest simultaneous and max for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a cb ratio of 0.28 ps/V at cb = 0 5 V. The BR CEO is 5.6 V and the devices fail thermally only at 18 mW m 2 , allowing dc bias from = 4 8 mA m 2 at ce = 3 9 V to = 12 5 mA m 2 at ce = 1 5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.
Wideband DHBTs using a graded carbon-doped InGaAs base
IEEE Electron Device Letters, 2000
We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT), fabricated using a mesa structure, exhibiting 282 GHz and 400 GHz max . The DHBT employs a 30 nm InGaAs base with carbon doping graded from 8 10 19 /cm 3 to 5 10 19 /cm 3 , an InP collector, and an InGaAs/InAlAs base-collector superlattice grade, with a total 217 nm collector depletion layer thickness. The low base sheet (580 ) and contact ( 10m 2 ) resistivities are in part responsible for the high max observed.
IEEE Electron Device Letters, 2011
We report an InP/In 0.53 Ga 0.47 As/InP double heterojunction bipolar transistor (DHBT) demonstrating simultaneous 430-GHz f τ and 800-GHz f max . The devices were fabricated using a triple mesa process with dry-etched refractory metals for emitter contact formation. The devices incorporate a 30-nm-thick InP emitter semiconductor which enables a wet-etch emitter process demonstrating 270-nm-wide emitter-base junctions. At peak RF performance, the device is operating at 30 mW/μm 2 with J c = 18.4 mA/μm 2 and V ce = 1.64 V. The devices show a peak DC common-emitter current gain (β) ∼ 20 and V BR,CEO = 2.5 V. Index Terms-Heterojunction bipolar transistor (HBT), indium phosphide (InP).
16th IPRM. 2004 International Conference on Indium Phosphide and Related Materials, 2004., 2004
Metamorphic InP/In/sub 0.53/Ga/sub 0.47//InP double heterojunction bipolar transistors (mHBT) were grown and fabricated. And f/sub /spl tau// and f/sub max/ of 268 and 339 GHz were measured, respectively - both records for mHBTs. The DC current gain /spl beta/ is /spl ap/ 35 and V/sub BR,CEO/ = 5.7 V. The collector leakage current I/sub cbo/ is 90 pA at V/sub cb/ = 0.3 V. A 70 nm SiO/sub 2/ dielectric sidewall was deposited on the emitter contact to permit a longer InP emitter wet etch and increase device yield. The metamorphic buffer layer is InP - employed because of its high thermal conductivity for minimum device thermal resistance.
Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process
IEEE Electron Device Letters, 2000
This letter reports InP/In 0.53 Ga 0.47 As/InP double heterojunction bipolar transistors (DHBTs) employing an N + subcollector and N + collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C cb associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N + subcollector that lies underneath the base ohmic contact, as well as compensate the ∼ 1 − 7 × 10 −7 C/cm 2 surface charge at the interface between the indium phosphide (InP) substrate and the N − collector drift layer. By implanting the subcollector, C cb associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C cb by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f τ and 403-GHz f max . The dc current gain β ≈ 38, BV ceo = 6.0 V, BV cbo = 5.4 V, and I cbo < 50 pA at V cb = 0.3 V. Index Terms-Collector pedestal, heterojunction bipolar transistor (HBT), indium phosphide (InP), ion implantation.
Solid-State Electronics, 2005
We have demonstrated InP/InGaAs/InP MBE-grown DHBTs fabricated with patterned sub-collector by elevated temperature 200°C N+ implant and subsequent device material over growth. F t /F max > 250 GHz/300 GHz were obtained on DHBTs with 0.35 lm · 6 lm emitters from this process. Ring oscillators fabricated with this process showed good uniformity with 82% of yield on wafers and an average gate delay of 8 ps. Difference of surface morphology on re-grown DHBT layers over elevated temperature implanted and room temperature 22°C implanted sub-collector was observed.
High-performance InP/In/sub 0.53/Ga/sub 0.47/As/InP double HBTs on GaAs substrates
IEEE Electron Device Letters, 2002
InP/In 0 53 Ga 0 47 As/InP double heterojunction bipolar transistors (HBTs) were grown on GaAs substrates. A 140 GHz power-gain cutoff frequency max and a 207 GHz current-gain cutoff frequency were obtained, presently the highest reported values for metamorphic HBTs. The breakdown voltage BV was 5.5 V, while the dc current gain was 76. High-thermal-conductivity InP metamorphic buffer layers were employed in order to minimize the device-thermal resistance.