Novel Reversible Variable Precision Multiplier Using Reversible Logic Gates (original) (raw)

Implementation of an 8-bit Low-power Multiplier based on Reversible Gate Technology

Reversible logic has attracted tremendous interest among the researchers in the low power VLSI field due to their simple structure and improved energy efficiency. In this paper, the implementation of an 8-bit low power multiplier based on reversible gate technology is reported. The structure of the reversible gate multiplier consists of the following components: the first part is the reversible partial product generator circuit (PPGC) which will be realized by a reversible AND gate; the second part is constructed of several TSG gates whose function is to add the carryout of the previous level and PPCG of current level together. In the second part, some XNOR gates and NOR gates with improved designs to save power and speed up the performance are presented. The 8-bit reversible gate multiplier is designed and simulated in PSPICE. PSPICE simulation verifies the correct function of the multiplier. In order for comparison, an 8-bit static CMOS multiplier is also designed. PSPICE power simulation is used to simulate the power consumption of both the reversible gate multiplier and the static CMOS multiplier for the same given input pattern sequence. Simulation results show that the reversible gate multiplier leads to effective power saving compared to the static CMOS multiplier.

Design and Simulation of a High Performance Multiplier using Reversible Gates

International Journal of Engineering Sciences & Research Technology, 2014

Multipliers are the significant part of the present technology as they are mostly used in the convolution, fast Fourier transform, CPU designing etc. The speed and power dissipation of the multiplier operation is the very important factor. The reversible logic design provide the low power dissipation hence the multiplier designed using the reversible logic gates provide the low power dissipation and also the high performance. In our design we use the reversible logic gates are BVPPG gate, BME gate and MHNG gate. Our design provides high performance and also dissipates the low power than any other reversible design.

An Area Efficient and High Speed Reversible Multiplier Using NS Gate

In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called " NSG(Non linear Sign Flip) ". The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.

Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates

International Journal of Computer Applications, 2014

Reversible logic is highly useful in nanotechnology, low power design and quantum computing. The paper proposes efficient MOS implementation for the basic reversible gates namely, Feynman, Toffoli, and Peres gates and employs the proposed circuits in the reversible binary multiplier design. It also juxtaposes the three proposed architectures to compare their properties and hence propose the most optimized form of the aforementioned multipliers.

Design of Low Power Reversible Multiplier

Madhina Basha, Arnnpalli Jaya Prakash & Karukola Girija, 2013

Reversible computing is a promising alternative to these technologies, with applications in ultra-low power, nano computing, quantum computing, low power CMOS design, optical information processing, bioinformatics etc. In reversible logic the power dissipation can be minimized or even eliminated. Power dissipation is one of the most important factor in the VLSI circuits design .In this paper a 4x4 reversible multiplier circuit is proposed with the design of two new reversible gates called ABC and GPS gates. In this paper the reversible multiplier circuit is designed by using GDI low power technique and is compared with conventional CMOS in terms of area and power. And this done by using Tannar tools.

Design of Efficient Reversible Multiplier

Reversible logic is emerging computing paradigm with applications in Ultra-low power Nano computing, quantum computing, Low power CMOS design, Optical Information Processing, Bioinformatics etc. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct NxN reversible multiplier circuit.

Design and Optimization of Reversible Multiplier Circuit

The development of conventional computing technologies faces many challenges for the last couple of decades. Power dissipation in today’s computer chips becomes dominant. Reversible computing is a promising alternative to these technologies, with applications in ultra-low power, nano computing, quantum computing, low power CMOS design, optical information processing, bioinformatics etc. In reversible logic the power dissipation can be minimized or even eliminated. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM gate. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct nxn reversible multiplier circuit.

Design And Performance Analysis Of Reversible Logic Four Quadrant Multiplier Using CSLA And CLAA

Multiplication is a fundamental operation in most signal processing algorithms. Multipliers have large area, long latency and consume considerable power. Therefore low-power multiplier design has been an important part in low-power VLSI system design. There has been extensive work on low-power multipliers at technology, physical, circuit and logic levels. A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. As a result, a whole spectrum of multipliers with different area-speed constraints has been designed with reversible logic gates. The reversible logic has the promising applications in emerging computing paradigm such as quantum computing, quantum dot cellular automata, optical computing, etc. In reversible logic gates there is a unique one-to-one mapping between the inputs and outputs.

Design and Implementation of Reversible Multiplier using optimum TG Full Adder

IOSR Journal of Electronics and Communication Engineering, 2017

The reversible logic has received great attention in last few years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design. Multipliers are widely used in DSP for calculation of FFT, convolution, to perform MAC operation, and in microprocessors to perform ALU related operations. This paper proposes a 16X16 reversible multiplier using Toffoli gate Full adder which can multiply two 16-bit numbers. It is based on the two concepts, the partial products are generated in parallel using Toffoli gates, and the addition of partial products is carried out by using reversible full adder designed with modified TG gate. The designed multiplier is faster and has low hardware complexity. In addition to that the designed reversible multiplier is better than the existing counterparts in terms of power consumption, delay, Garbage inputs, outputs, and quantum cost. The designed 16-bit multiplier is modeled using Verilog HDL and functionality is verified with Xilinx Vivado 2016.2.

Analysis of Multiplier Circuit Using Reversible Logic

Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. Reversible circuits hold promise in futuristic computing technologies like low power VLSI, quantum computing, nanotechnology, optical computing etc. Reversible gates require constant inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. It is important to minimize parameters such as constant and garbage bits, quantum cost and delay in the design of reversible circuits. In this paper, new multiplier using Toffoli gate, Peres gate, Double Peres gate is proposed for minimization of constant input, garbage output, quantum cost.