Compiling polychronous programs into conditional partial orders for ASIP synthesis (original) (raw)

Conditional Partial Order Graphs: Model, Synthesis, and Application

IEEE Transactions on Computers, 2000

The paper introduces a new formal model for specification and synthesis of control paths in the context of asynchronous system design. The model, called Conditional Partial Order Graph (CPOG), captures concurrency and choice in a system's behavior in a compact and efficient way. It has advantages over widely used interpreted Petri Nets and Finite State Machines for a class of systems which have many behavioral scenarios defined on the same set of actions, e.g., CPU microcontrollers. The CPOG model has potential applications in the area of microcontrol synthesis and brings new methods for modeling concurrency into the application domain of modern and future processor architectures. The paper gives the formal definition of the CPOG model, formulates and solves the problem of CPOG synthesis, and introduces various optimization techniques. The presented ideas can be applied for CPU control synthesis as well as for synthesis of different kinds of event-coordination circuits often used in data coding and communication in digital systems, as demonstrated with several application examples.

Towards Parallel Boolean Functional Synthesis

Tools and Algorithms for the Construction and Analysis of Systems

Given a relational specification ϕ(X, Y), where X and Y are sequences of input and output variables, we wish to synthesize each output as a function of the inputs such that the specification holds. This is called the Boolean functional synthesis problem and has applications in several areas. In this paper, we present the first parallel approach for solving this problem, using compositional and CEGAR-style reasoning as key building blocks. We show by means of extensive experiments that our approach outperforms existing tools on a large class of benchmarks.

Using Answer Set Programming Solvers to Synthesize Concurrent Programs

Research Report Series of Iasi Cnr Rome Italy, 2012

We address the problem of the automatic synthesis of concurrent programs within a framework based on Answer Set Programming (ASP). Every concurrent program to be synthesized is specified by providing both the behavioural and the structural properties it should satisfy. Behavioural properties, such as safety and liveness properties, are specified by using formulas of the Computation Tree Logic, which are encoded as a logic program. Structural properties, such as the symmetry of processes, are also encoded as a logic program. Then, the program which is the union of these two encoding programs, is given as input to an ASP system which returns as output a set of answer sets. Finally, each answer set is decoded into a synthesized program that, by construction, satisfies the desired behavioural and structural properties. 4. proofs of the results presented in the paper, and the ASP source code of our synthesis procedure. 2. Preliminaries Let us recall some basic notions and terminology we will use. We will present: (i) the syntax of (a variant of) the guarded commands [10], which we use for defining concurrent programs, (ii) some basic notions of group theory, which are required for defining symmetric concurrent programs, and (iii) some fundamental concepts of Computation Tree Logic and of Answer Set Programming, which we use for our synthesis method. 2.1. Guarded commands The guarded commands we consider are defined from the following two basic sets: (i) variables, v in Var , each ranging over a finite domain D v , and (ii) guards, g in Guard , of the form: g ::= true | false | v = d | ¬ g | g 1 ∧ ∧ g 2 , with v ∈ Var and d ∈ D v. We also have the following derived sets whose definitions are mutually recursive: (iii) commands, c in Command , of the form: c ::= skip | v := d | c 1 ; c 2 | if gc fi | do gc od , where ';' denotes the sequential composition of commands which is associative, and (iv) guarded commands, gc in GCommand , of the form: gc ::= g → c | gc 1 gc 2 , where ' ' denotes the parallel composition of guarded commands which is associative and commutative. The operational semantics of commands can be described in an informal way as follows. skip does nothing. v := d stores the value d in the location of the variable v. In order to execute c 1 ; c 2 the command c 1 is executed first, and then the command c 2 is executed. In order to execute if gc 1. .. gc n fi, with n ≥ 1, one of the guarded commands g → c in {gc 1 ,. .. , gc n } whose guard g evaluates to true, is chosen, and then c is executed; otherwise, if no guard of a guarded command in {gc 1 ,. .. , gc n } evaluates to true, then the whole command if. .. fi terminates with failure. In order to execute do gc 1. .. gc n od, with n ≥ 1, one of the guarded commands g → c in {gc 1 ,. .. , gc n } whose guard g evaluates to true, is chosen, then c is executed and the whole command do. .. od is executed again; otherwise, if no guard of a guarded command in {gc 1 ,. .. , gc n } evaluates to true, then the execution proceeds with the next command. The formal semantics of commands will be given in the next section. 2.2. Groups A group G is a pair S , • , where S is a set and • is a binary operation on S satisfying the following axioms: (i) ∀x, y ∈ S. x•y ∈ S, (ii) ∀x , y, z ∈ S. (x •y)•z = x •(y •z), (iii) ∃e ∈ S. ∀x ∈ S. e•x = x•e = x, and (iv) ∀x ∈ S. ∃y ∈ S. x•y = y•x = e. The element e is the identity of the group G and the cardinality of S is the order of the group G. For any x ∈ S, for any n ≥ 0, we write x n to denote the term x•.. .•x with n occurrences of x. We stipulate that x 0 is e. A group G = S , • is said to be cyclic iff there exists an element x ∈ S, called a generator, such that S = {x n | n ≥ 0}. We denote by Perm(S) the set of all permutations on the set S, that is, the set of all bijections from S to S. Perm(S) is a group whose operation • is function composition and the identity e is the identity permutation, denoted id. Given a finite set S, the order of a permutation p in Perm(S) is the smallest natural number n such that p n = id. 5. 2.3. Computation Tree Logic Computation Tree Logic (CTL) is a propositional branching time temporal logic [8]. The underling time structure is a tree of states. Every state denotes an instant in time and may have many successor states. There are quantifiers over paths of the tree: A (for all paths) and E (for some path), which are used for specifying properties that hold for all paths or for some path, respectively. Together with these quantifiers, there are temporal operators such as: X (next state), F (eventually), G (globally), and U (until), which are used for specifying properties that hold in the states along paths of the tree. Their formal semantics will be given below. Given a finite nonempty set Elem of elementary propositions ranged over by p, the syntax of CTL formulas ϕ is as follows: ϕ ::= p | ϕ 1 ∧ ∧ ϕ 2 | ¬ϕ | EX ϕ | EG ϕ | E[ϕ 1 U ϕ 2 ] We introduce the following abbreviations: (i) true for ϕ ∨ ∨ ¬ϕ, where ϕ is any CTL formula, (ii) false for ¬true, (iii) ϕ 1 ∨ ∨ ϕ 2 for ¬(¬ϕ 1 ∧ ∧ ¬ϕ 2), (iv) EFϕ for E[true U ϕ] (v) AG ϕ for ¬EF ¬ϕ, (vi) AF ϕ for ¬EG ¬ϕ, (vii) A[ ϕ 1 Uϕ 2 ] for ¬E[¬ϕ 2 U (¬ϕ 1 ∧ ∧ ¬ϕ 2)] ∧ ∧ AF ϕ 2 , and (viii) AX ϕ for ¬EX ¬ ϕ. The semantics of CTL is provided by a Kripke structure K = S, S 0 , R, λ , where: (i) S is a finite set of states, (ii) S 0 ⊆ S is a set of initial states, (iii) R ⊆ S × S is a total transition relation (thus, ∀u ∈ S. ∃v ∈ S. u, v ∈ R), and (iv) λ : S → P(Elem) is a total labelling function that assigns to every state s ∈ S a subset λ(s) of the set Elem. A path π in K from a state s 0 is an infinite sequence s 0 , s 1 ,. .. of states such that, for all i ≥ 0, s i , s i+1 ∈ R. The fact that a CTL formula ϕ holds in a state s of a Kripke structure K will be denoted by K, s ϕ. For any CTL formula ϕ and state s, we define the relation K, s ϕ as follows: K,s p iff p ∈ λ(s) K,s ¬ ϕ iff K,s ϕ does not hold K,s ϕ 1 ∧ ∧ ϕ 2 iff K,s ϕ 1 and K,s ϕ 2 K,s EX ϕ iff there exists s, t ∈ R such that K,t ϕ K,s E[ϕ 1 U ϕ 2 ] iff there exists a path s 0 ,s 1 ,s 2 ,.. . in K with s 0 = s such that for some i ≥ 0, K,s i ϕ 2 and for all 0 ≤ j < i, K,s j ϕ 1 K,s EG ϕ iff there exists a path s 0 ,s 1 ,s 2 ,.. . in K with s 0 = s such that for all i ≥ 0, K,s i ϕ.

Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis

2008 Design, Automation and Test in Europe, 2008

The paper introduces a new formal model for specifying control paths in the context of asynchronous system design. The model, called Conditional Partial Order Graph (CPOG), is capable of capturing concurrency and choice in a system's behaviour in a compact and ecient way. A problem of synthesis of a CPOG composition from a set of given CPOGs is formulated and solved in this paper in respect of a subclass of CPOGs that are partial orders. This problem can be extended to a more general class of CPOGs, which is subject to future research.

Generating fast code from concurrent program dependence graphs

ACM SIGPLAN Notices, 2004

While concurrency in embedded systems is most often supplied by real-time operating systems, this approach can be unpredictable and difficult to debug. Synchronous concurrency, in which a system marches in lockstep to a global clock, is conceptually easier and potentially more efficient because it can be statically scheduled beforehand.

Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design

2010 10th International Conference on Application of Concurrency to System Design, 2010

ABSTRACT There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of instructions. The method is based on the Conditional Partial Order Graph (CPOG) model introduced recently, which is a formalism for efficient specification and synthesis of microcontrol circuits. It describes a system as a functional composition of its behavioural scenarios, or instructions, each of them being a partial order of events. In order to distinguish instructions within a CPOG they are given different encodings represented with Boolean vectors. Size and latency of the final microcontroller significantly depends on the chosen encodings, thus efficient synthesis of instruction codes is essential. This paper presents a method for optimal encoding of a given set of partial orders so that a CPOG containing all of them has the minimum complexity, thereby leading to the smallest and fastest controller.

A structural encoding technique for the synthesis of asynchronous circuits

2001

This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is always guaranteed. Moreover, a set of transformations is presented for the subclass of Free-Choice Petri nets that enables the exploration of different solutions. All transformations preserve the property of free-choiceness, thus enabling the use of structural methods for the synthesis of asynchronous circuits. Preliminary experimental results indicate that the quality of the circuits is comparable to that obtained by methods that require an exhaustive enumeration of the state space.