Towards an open embedded system on chip for network applications (original) (raw)

Opencores based Embedded System on Chip for Network Applications

The System-on-Chip (SoC) refers to a mini computer independent system where all essential parts of computing are integrated into a single FPGA or ASIC chip and where the application is executed by a program, which is loaded into an on chip memory or an off shelf component. However the increasing complexity of embedded systems and the staggering costs associated with designing systems-on-chip imposes system designer and companies to seek collaboration on a variety of intellectual property issues. Consequently the cost of building SoC is increasing significantly when the system integrates several parts. This paper presents Hardware/Software development of an embedded system on chip for network application, based on the Opencores and Opensources design concepts, in order to build an embedded systemon-chip for network applications at free cost. This approach is based on the IP (Intellectual Property) reuse strategy which facilitates the rapid creation and verification design process. In this paper we define the methodology adopted to construct our SoC. The system includes a hardware part and a software part which are linked to each other through a µClinux operating system. For the hardware part, an HDL file describing all the cores of the library is created. The SoC architecture is mapped into the virtex5 XC5VLX50-1FF676 FPGA development board. Results show that the SoC architecture occupies 27% of logic resources and 35% of IOBs (In/Out Blocs). The software development of the embedded network application includes two parts: Configuration and compilation of the µClinux and programming of network application. In this part we have chosen an embedded network TFTP (trivial file transfer protocol) client as a test application. The results of the software part shows that the boot of µClinux and TFTP client test under the Or1ksim which is an instruction set simulator as well as the frame transfers were successfully done.

Platform Based on Open-Source Cores for Industrial Applications

2004

The latest version of the International Technology Roadmap for Semiconductors predicts that design reuse will be essential in the near future to face the constantly increasing design complexity. The concept comes from software engineering in which reuse is a fundamental technology. In order to provide libraries and applications to reuse in software development, some open-source initiatives (e.g. Linux, gcc, X, mysql) have appeared during the last decades. The basic idea is to distribute the library or application source code (normally free-ofcharge) and allow any developer to use, modify, debug and improve it. Several initiatives have tried to port this idea to hardware development. The main goal of this paper is to develop a synthesizable platform described in SystemC from an open architecture. The platform includes a CPU (OpenRISC) and some basic peripherals. A set of software development tools (compiler, assembler, debugger) and RTOS (eCos) has also been developed. This work enables the evaluation of the advantages and disadvantages of the open-source model in electronic system design.

An open platform for developing multiprocessor SoCs

Computer, 2005

We plan to introduce this platform in consumer and telecommunications product development to increase software and hardware engineers' productivity. This will reduce development time and costs while ensuring design and product quality. EMULATION AND DESIGN METHODOLOGIES An emulation platform is a hardware system used to map a hardware design. It can run at one-to A low-cost modular approach that uses emulation offers an alternative to software simulation for the design and verification of complex multiprocessor system-on-chip (MPSoC) designs.

Using open source cores in real applications

2003

Design reuse plays an important role in the current design process and it will be essential in the near future to face the constantly increasing design complexity as predicted in the latest version of the International Technology Roadmap for Semiconductors. The concept comes from software engineering in which reuse is a fundamental technology. Today, reused libraries are common components in any software program and they have allowed an enormous reduction of the software development cost. In order to provide libraries and applications to support software development, open-source initiatives have appeared during the last decades. The basic idea is to distribute the library or application source code (normally free-of-charge) and allow any developer to use, modify, debug and improve it. Very important applications (e.g. Linux, gcc, Apache) and libraries (e.g. X, gdbm, mysql) have been developed with this model. Several initiatives have tried to port this idea to hardware development. The main goal of this paper is to evaluate the advantages and disadvantages of the open-source model in electronic system design. From an open architecture, a synthesizable platform (described on SystemC) has been developed. The platform includes a CPU (OpenRISC) and some basic peripherals, such as a bus controller, watchdog and UART. A set of software development tools (compiler, assembler, debugger) and RTOS (eCos) has also been developed.

Towards Reuse-Based Development for the On-chip Distributed SoC Architecture

2012 IEEE 36th Annual Computer Software and Applications Conference Workshops, 2012

The development of a reusable library of components for a multi-core segmented bus platform, the SegBus, is presented. The library is based on a plug-in that we develop and deploy within a modeling tool which eventually used by the SegBus DSL while developing applications targeting the SegBus platform. The steps required in building the library and embed it into a plug-in are discussed together with the certain use of it in our design methodology.

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, 2006

The constant increase of gate capacity and performance of configurable hardware chips made it possible to implement systems-on-chip (SoC) able to tackle the demanding requirements of many embedded systems. In this paper, we propose an approach to the design space exploration of a configurable SoC (CSoC) platform based on a network on chip (NoC) architecture for the execution of dataflow dominated embedded systems. The approach has been validated with the design of a color image compression algorithm in an FPGA.

Networks on chip as hardware components of an os for reconfigurable systems

… Logic and Applications, 2003

Abstract. In complex reconfigurable SoCs, the dynamism of applica-tions requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC plat-forms should be developed together. The operating system ...

Extending Platform-Based Design to Network on Chip Systems

2003

Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOCbased systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods. Workload modeling Simulation Architecture modeling Software development Simulation Architecture modeling Workload modeling and mapping Simulation Architecture modeling Requirements and restrictions Network-level SoC-level Processor-level Decision support

A SDN Solution for System-on-Chip World

—System on chips (SoCs) are all around us in today's world. Therefore, in this paper we propose a flexible, technology-aware SoC design, named as Cloud-of-Chips (CoC), which is able to change its characteristics, such as routing logic, transmission paths, priorities, IC clustering, etc. We focus particularly on inside communication of CoC architecture. The basic idea of CoC is the creation of an architecture, which will be able to support all the requirements of a vast number of todays applications by adopting and changing its characteristics according to them. The valorization perspectives are of importance since the outcomes of this research will be applicable for embedded systems, real-time systems, communication systems, as well as for mainstream systems such as Internet-of-Things and Internet-of-Everything. As far as the inside communication of our CoC platform is concerned, we leverage on algorithms and strategies developed within the field of Software Defined Networking (SDN), which was introduced to deal with hardware redesign and ultimately provide cloud-like flexibility. At the end, we describe registration and authentication of every entity in our network.

On-chip networks: A scalable, communication-centric embedded system design paradigm

VLSI Design, 2004. …, 2004

As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts. More and more processor cores and large, reusable components are being integrated on a single silicon die but reuse of the communication infrastructure has been difficult. Buses and point to point connections, that have been the main means to connect components on a chip today, will not result in a scalable platform architecture for the billion transistor chip era. Buses can cost efficiently connect a few tens of components. Point to point connections between communication partners is practical for even fewer components. As more and more components are integrated on a single silicon die, performance bottlenecks of long, global wires preclude reuse of buses. Therefore, scalable on-chip communication infrastructure is playing an increasingly dominant role in system-onchip designs. With the super-abundance of cheap, functionspecific IP cores, design effort will focus on the weakest link: efficient on-chip communication. Future on-chip communication infrastructure will overcome the limits of bus-based systems by providing higher bandwidth, higher flexibility and by solving the clock skew problem on large chips. It may, however, present new problems: higher power consumption of the communication infrastructure and harder-to-predict performance patterns. Solutions to these problems may result in a complete overhaul of SOC design methodologies into a communication-centric design style. The envisioning of upcoming problems and possible benefits has led to intensified research in the field of what is called NoCs: Networks on Chips. The term NoCs is used in a broad meaning, encompassing the hardware communication infrastructure, the middleware and operating system communication services, and a design methodology and tools to map applications onto a network on chip. This paper discusses trends in system-on-chip designs, critiques problems and opportunities of the NoC paradigm, summarizes research activities, and outlines several directions for future research.